Datasheet > SNC21300A

SNC21300A

更新时间： 2022-12-29 05:30:47

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SNC21300A 数据手册

SNC21300A

1-CH H.Q. Speech Controller

Port

Data

Port

Status

Wea

To Internal Data Bus

Read Control

I/O Port Configuration

Note:

(1) Weak N-MOS can serve as pull-low resistor.

(2) The driving/sink current of P3.3 ~ P3.2 & P4.0~P4.3 is up to 8mA/16mA

5.8 IR Function

Bit 3 of Mode Register is applied to control the IR function. P33 can be modulated with

38.5KHz square wave before sent out to P3.3 or P2.3 pin. P3.3 and P2.3 out is

controlled by Mode1.1. If Mode1.1 set 1 IR is use P2.3, set “0” is use P3.3. The IR

signal can be achieved by this modulated signal.

5.9 PWM IO control

SNC21300A has support 6 PWM IO (P3.0~P3.3 & P6.0~P6.1). Each I/O has 8 bit

independent duty register, and the 8 bit register are compare with 8 bits counter. If set

use PWM IO function and internal counter start at 000H, the mapping I/O will set High.

The 8 bits counter increment if the same duty-register, that will reset the mapping IO

pin.

5.10 Watch Dog Timer

SNC21300A built-in an internal WDT (Watch Dog Timer). This Watchdog timer would

issue resets signal to this chip if it is not cleared before reaching terminal count (128

ms). The watchdog timer is enabled at reset and cannot be disabled.

Ver1.1

November 6, 2009

1...3 4 567 8 9...12

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