Datasheet > SNC21300A

SNC21300A

更新时间： 2022-12-29 05:30:47

品牌	Logo	应用领域
松翰 - SONIX		控制器
页数	文件大小	规格书
12页	129K
描述
1-CH H.Q. Speech Controller

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SNC21300A 数据手册

SNC21300A

1-CH H.Q. Speech Controller

5. FUNCTION DESCRIPTIONS

5.1 Oscillator

System clock define 2MHz, the source provided by external resistor ring oscillator.

5.2 ROM

SNC21300A contains a substantial maximum 912K words (10-bit) internal ROM,

which is shared by program and resource data. Program, voice and data are shared

within this same 912K words ROM.

5.3 RAM

SNC21300A contains maximum 128 nibble RAM (128 x 4-bits). The 128 nibble RAM

is divided into eight pages (page 0 to page 7, 16 nibble RAM on each page). In our

programming structure, users can use the instructions, PAGE n (n=0 to 7) to switch

and indicate the RAM page. Besides, users can use direct mode, M0 ~ M15 in the

data transfer type instructions, to access all 16 nibbles of each page.

5.4 Power Down Mode

“End” instruction makes the IC entering into Stop Mode will stop the system clock for

power savings (<3uA @VDD=3V and <6uA @VDD=4.5V.) Any valid data transition

(LꢂH or HꢂL) occurring on any IO pin can be used to start the system clock and

return to normal operating mode.

5.5 Sampling Rate Counter

The unique sampling rate counter is designed in voice channel to be able to play

diverse voices at different sample playing rates. The playing rate can be adaptively

set up among from the wide ranges of 2.5KHz to 20KHz. This architecture yields a

high-quality voice synthesis that sounds very close to its original source when played

through the same amplifier and speaker circuitry.

5.6 Auto Repeat Function

A voice section can be repeated by the built-in special hardware of SNC21300A

without any software effort. The function activated by setting the corresponding bit of

a control register. Once the control register was setting, the channel will continue to

play the voice section (the Next Section).

5.7 I/O Ports

There are six 4-bit I/O ports P1, P2, P3, P4, P5 and P6. Any I/O can be individually

programmed as either input pull low or output. Any valid data transition (Hꢂ L or

LꢂH) of P1, P2, P3, P4, P5 and P6 can reactivate the chip when it is in power-down

stage.

Ver1.1

November 6, 2009

1 2 3 456 7 8...12

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