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SN74LVTH16245ADGG PDF预览

SN74LVTH16245ADGG

更新时间： 2023-02-15 00:00:00
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件
页数 文件大小 规格书
8页 107K
描述
LVT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, TSSOP-48

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SN74LVTH16245ADGG 数据手册

 浏览型号SN74LVTH16245ADGG的Datasheet PDF文件第2页浏览型号SN74LVTH16245ADGG的Datasheet PDF文件第3页浏览型号SN74LVTH16245ADGG的Datasheet PDF文件第4页浏览型号SN74LVTH16245ADGG的Datasheet PDF文件第5页浏览型号SN74LVTH16245ADGG的Datasheet PDF文件第6页浏览型号SN74LVTH16245ADGG的Datasheet PDF文件第7页 
SN54LVTH16245A, SN74LVTH16245A  
3.3-V ABT 16-BIT BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS143L – MAY 1992 – REVISED APRIL 1999  
SN54LVTH16245A . . . WD PACKAGE  
SN74LVTH16245A . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
3
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
4
5
3.3-V V  
)
CC  
6
Support Unregulated Battery Operation  
Down to 2.7 V  
7
V
V
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Flow-Through Architecture Optimizes PCB  
Layout  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2DIR  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The ’LVTH16245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage  
(3.3-V) V operation, but with the capability to provide a TTL interface to a 5-V system environment.  
CC  
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission  
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control  
(DIR) input. The output-enable (OE) input can be used to disable the devices so that the buses are  
effectively isolated.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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