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SN74LVTH162541DGG PDF预览

SN74LVTH162541DGG

更新时间： 2024-11-22 22:36:35
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
7页 106K
描述
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74LVTH162541DGG 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP,
针数：48Reach Compliance Code：compliant
风险等级：5.61其他特性：WITH DUAL OUTPUT ENABLE
系列：LVTJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：250传播延迟（tpd）：4.7 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

SN74LVTH162541DGG 数据手册

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SN54LVTH162541, SN74LVTH162541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS690E – MAY 1997 – REVISED APRIL 1999  
SN54LVTH162541 . . . WD PACKAGE  
SN74LVTH162541 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1OE1  
1Y1  
1OE2  
1A1  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
1Y2  
1A2  
Output Ports Have Equivalent 22-Ω Series  
Resistors, So No External Resistors Are  
Required  
GND  
1Y3  
GND  
1A3  
1Y4  
1A4  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
V
V
CC  
CC  
1Y5  
1Y6  
1A5  
1A6  
3.3-V V  
)
CC  
GND 10  
1Y7 11  
39 GND  
38 1A7  
Support Unregulated Battery Operation  
Down to 2.7 V  
1Y8  
1A8  
12  
37  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
2Y1 13  
2Y2 14  
GND 15  
2Y3 16  
2Y4 17  
36 2A1  
35 2A2  
34 GND  
33 2A3  
32 2A4  
= 3.3 V, T = 25°C  
CC  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
V
18  
31  
V
CC  
CC  
2Y5 19  
2Y6 20  
GND 21  
2Y7 22  
2Y8 23  
2OE1 24  
30 2A5  
29 2A6  
28 GND  
27 2A7  
26 2A8  
25 2OE2  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable  
signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must  
be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit  
buffer section are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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