SN54/74LS74A
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-
cuitry to produce high speed D-type flip-flops. Each flip-flop has individual
clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going
edge of the clock pulse. Clock triggering occurs at a voltage level of the clock
pulse and is not directly related to the transition time of the positive-going
pulse. When the clock input is at either the HIGH or the LOW level, the D input
signal has no effect.
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
LOGIC DIAGRAM (Each Flip-Flop)
CASE 632-08
14
1
SET (S
)
D
4 (10)
Q
5 (9)
CLEAR (CD)
1 (13)
N SUFFIX
PLASTIC
CASE 646-06
CLOCK
3 (11)
14
Q
6 (8)
1
D
2 (12)
D SUFFIX
SOIC
CASE 751A-02
14
1
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
MODE SELECT — TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
S
D
S
D
D
Q
Q
Set
L
H
L
H
H
H
L
L
H
H
X
X
X
h
l
H
L
H
H
L
L
H
H
L
LOGIC SYMBOL
Reset (Clear)
*Undetermined
Load “1” (Set)
Load “0” (Reset)
4
10
H
S
S
D
D
5
6
9
8
2
3
D
Q
Q
12
11
D
Q
Q
* Both outputs will be HIGH while both S and C are LOW, but the output states are unpredictable
D
D
if S and C goHIGHsimultaneously. If the levels at the set and clear are near V maximumthen
D
D
IL
CP
CP
we cannot guarantee to meet the minimum level for V
.
OH
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
C
C
D
D
1
13
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
i, h (q) = prior to the HIGH to LOW clock transition.
V
= PIN 14
CC
GND = PIN 7
FAST AND LS TTL DATA
5-72