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SN74LS17DR PDF预览

SN74LS17DR

更新时间: 2024-09-21 19:55:23
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
14页 888K
描述
LS SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14, PLASTIC, MS-012AB, SOIC-14

SN74LS17DR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82系列:LS
JESD-30 代码:R-PDSO-G14长度:8.65 mm
负载电容(CL):15 pF逻辑集成电路类型:BUFFER
功能数量:6输入次数:1
端子数量:14最高工作温度:70 °C
最低工作温度:输出特性:OPEN-COLLECTOR
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
最大电源电流(ICC):45 mA传播延迟(tpd):30 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

SN74LS17DR 数据手册

 浏览型号SN74LS17DR的Datasheet PDF文件第2页浏览型号SN74LS17DR的Datasheet PDF文件第3页浏览型号SN74LS17DR的Datasheet PDF文件第4页浏览型号SN74LS17DR的Datasheet PDF文件第5页浏览型号SN74LS17DR的Datasheet PDF文件第6页浏览型号SN74LS17DR的Datasheet PDF文件第7页 
ꢉꢊꢋ ꢌꢍꢎ ꢎ ꢊꢏꢀꢐ ꢑ ꢏꢒ ꢓ ꢊꢏ  
The SN54LS07 and SN74LS17 are  
obsolete and are no longer supplied.  
ꢗꢊ  
SDLS021C − MAY 1990 − REVISED FEBRUARY 2004  
SN54LS07 . . . J PACKAGE  
SN74LS07, SN74LS17 . . . D, DB, N, OR NS PACKAGE  
(TOP VIEW)  
D
D
D
D
Convert TTL Voltage Levels to MOS Levels  
High Sink-Current Capability  
Input Clamping Diodes Simplify System  
Design  
1A  
1Y  
2A  
2Y  
3A  
1
2
3
4
5
6
7
14  
V
CC  
13 6A  
12 6Y  
11 5A  
10 5Y  
Open-Collector Driver for Indicator Lamps  
and Relays  
description/ordering information  
3Y  
GND  
9
8
4A  
4Y  
These hex buffers/drivers feature high-voltage  
open-collector outputs to interface with high-level  
circuits or for driving high-current loads. They are  
also characterized for use as buffers for driving TTL inputs. The ’LS07 devices have a rated output voltage of  
30 V, and the SN74LS17 has a rated output voltage of 15 V. The maximum sink current is 30 mA for the  
SN54LS07 and 40 mA for the SN74LS07 and SN74LS17.  
These circuits are compatible with most TTL families. Inputs are diode-clamped to minimize transmission-line  
effects, which simplifies design. Typical power dissipation is 140 mW, and average propagation delay time is  
12 ns.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube  
SN74LS07N  
SN74LS07N  
Tube  
SN74LS07D  
SOIC − D  
SOP − NS  
LS07  
Tape and reel  
Tape and reel  
SN74LS07DR  
SN74LS07NSR  
SN74LS07DBR  
0°C to 70°C  
74LS07  
LS07  
SSOP − DB Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB  
design guidelines are available at www.ti.com/sc/package.  
logic diagram (positive logic)  
2
4
1
3
1A  
2A  
3A  
4A  
5A  
6A  
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
6
5
9
8
10  
12  
11  
13  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢖ ꢝ ꢨ ꢠ ꢟꢫ ꢦꢥ ꢣꢤ ꢥꢟ ꢡꢨ ꢪꢜ ꢢꢝ ꢣ ꢣꢟ ꢲꢒ ꢄꢘ ꢗꢏ ꢎ ꢘꢳꢴꢂ ꢳꢂꢇ ꢢꢪꢪ ꢨꢢ ꢠ ꢢ ꢡꢧ ꢣꢧꢠ ꢤ ꢢ ꢠ ꢧ ꢣꢧ ꢤꢣꢧ ꢫ  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
ꢦ ꢝꢪ ꢧꢤꢤ ꢟ ꢣꢭꢧ ꢠ ꢯꢜ ꢤꢧ ꢝ ꢟꢣꢧ ꢫꢬ ꢖ ꢝ ꢢꢪ ꢪ ꢟ ꢣꢭꢧ ꢠ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢤ ꢇ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢜꢟ ꢝ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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