ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢆꢈ ꢉꢆ
ꢊ
ꢋ
ꢀ
ꢌ
ꢀ
ꢍ
ꢛ
ꢎ
ꢔ
ꢏ
ꢇ
ꢐ
ꢄ
ꢑ
ꢝ
ꢏ
ꢃ
ꢛ
ꢑ
ꢒ
ꢇ
ꢓ
ꢋ
ꢍ
ꢇ
ꢔ
ꢕ
ꢍ
ꢒ
ꢖ
ꢒ
ꢗ
ꢘ
ꢊ
ꢔꢇ ꢝ ꢉ ꢏꢚ ꢇꢐ ꢍ ꢒꢗꢌꢁꢇ ꢍ ꢒꢚꢒ ꢍ ꢀ ꢝꢔ ꢑꢇ ꢒꢗ
ꢒ
ꢓ
ꢋ
ꢍ
ꢇ
ꢔ
ꢕ
ꢍ
ꢒ
ꢖ
ꢒ
ꢗ
ꢈ
ꢙ
ꢉ
ꢏ
ꢚ
ꢘ
ꢆ
ꢙ
ꢆ
ꢏ
ꢚ
ꢍ
ꢐ
ꢛ
ꢏ
ꢚ
ꢐ
ꢍ
ꢇ
ꢌ
ꢜ
ꢒ
ꢅ
ꢋ
SCDS148 − OCTOBER 2003
D
D
Output Voltage Translation Tracks V
D
D
V
Operating Range From 2.3 V to 3.6 V
CC
CC
Supports Mixed-Mode Signal Operation On
All Data I/O Ports
− 5-V Input Down To 3.3-V Output Level
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D
D
D
D
Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
Shift With 3.3-V V
CC
− 5-V/3.3-V Input Down To 2.5-V Output
Level Shift With 2.5-V V
I
Supports Partial-Power-Down Mode
off
CC
Operation
D
D
D
D
D
D
5-V Tolerant I/Os With Device Powered-Up
or Powered-Down
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bidirectional Data Flow, With Near-Zero
Propagation Delay
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
Low ON-State Resistance (r
)
on
Characteristics (r = 5 Ω Typical)
on
− 1000-V Charged-Device Model (C101)
Low Input/Output Capacitance Minimizes
D
D
Supports Digital Applications: Level
Translation, USB Interface, Memory
Interleaving, Bus Isolation
Loading (C
= 5 pF Typical)
io(OFF)
Data and Control Inputs Provide
Undershoot Clamp Diodes
Ideal for Low-Power Portable Equipment
Low Power Consumption
(I
= 20 µA Max)
CC
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
2OE
S0
2B4
2B3
2B2
2B1
2A
1OE
S1
CC
1B4
1B3
1B2
1B1
1A
GND
description/ordering information
The SN74CB3T3253 is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state
resistance (r ), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation
on
on all data I/O ports by providing voltage translation that tracks V . The SN74CB3T3253 supports systems
CC
using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels
(see Figure 1).
The SN74CB3T3253 is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable (1OE,
2OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When OE is low,
the associated multiplexer/demultiplexer is ON, and the A port is connected to the B port, allowing bidirectional
data flow between ports. When OE is high, the associated multiplexer/demultiplexer is OFF, and a
high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢕ
ꢕ
ꢗ
ꢐ
ꢭ
ꢊ
ꢨ
ꢋ
ꢄ
ꢦ
ꢇ
ꢧ
ꢔ
ꢡ
ꢐ
ꢟ
ꢁ
ꢠ
ꢊ
ꢌ
ꢇ
ꢌ
ꢞ
ꢟ
ꢩ
ꢠ
ꢡ
ꢧ
ꢢ
ꢣ
ꢤ
ꢤ
ꢥ
ꢥ
ꢞ
ꢞ
ꢡ
ꢡ
ꢟ
ꢟ
ꢞ
ꢦ
ꢦ
ꢪ
ꢧ
ꢨ
ꢢ
ꢢ
ꢩ
ꢩ
ꢟ
ꢥ
ꢤ
ꢣ
ꢦ
ꢦ
ꢡ
ꢠ
ꢪ
ꢇꢩ
ꢨ
ꢫ
ꢦ
ꢬ
ꢞ
ꢧ
ꢤ
ꢦ
ꢥ
ꢞ
ꢥ
ꢡ
ꢢ
ꢟ
ꢨ
ꢭ
ꢤ
ꢟ
ꢥ
ꢥ
ꢩ
ꢦ
ꢙ
Copyright 2003, Texas Instruments Incorporated
ꢢ
ꢡ
ꢧ
ꢥ
ꢡ
ꢢ
ꢣ
ꢥ
ꢡ
ꢦ
ꢪ
ꢞ
ꢠ
ꢞ
ꢧ
ꢩ
ꢢ
ꢥ
ꢮ
ꢥ
ꢩ
ꢢ
ꢡ
ꢠ
ꢯ
ꢤ
ꢔ
ꢟ
ꢣ
ꢩ
ꢦ
ꢥ
ꢤ
ꢟ
ꢭ
ꢤ
ꢢ
ꢭ
ꢰ
ꢤ
ꢥ ꢩ ꢦ ꢥꢞ ꢟꢲ ꢡꢠ ꢤ ꢬꢬ ꢪꢤ ꢢ ꢤ ꢣ ꢩ ꢥ ꢩ ꢢ ꢦ ꢙ
ꢢ
ꢢ
ꢤ
ꢟ
ꢥ
ꢱ
ꢙ
ꢕ
ꢢ
ꢡ
ꢭ
ꢨ
ꢧ
ꢥ
ꢞ
ꢡ
ꢟ
ꢪ
ꢢ
ꢡ
ꢧ
ꢩ
ꢦ
ꢦ
ꢞ
ꢟ
ꢲ
ꢭ
ꢡ
ꢩ
ꢦ
ꢟ
ꢡ
ꢥ
ꢟ
ꢩ
ꢧ
ꢩ
ꢦ
ꢦ
ꢤ
ꢢ
ꢞ
ꢬ
ꢱ
ꢞ
ꢟ
ꢧ
ꢬ
ꢨ
ꢭ
ꢩ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265