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SN74AS866ADW PDF预览

SN74AS866ADW

更新时间： 2024-10-01 19:55:03
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路
页数 文件大小 规格书
7页 113K
描述
8-Bit Magnitude Comparators with Input and Output Latches 28-SOIC 0 to 70

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中文翻译

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SN74AS866ADW 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：,
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.88
逻辑集成电路类型：MAGNITUDE COMPARATOR峰值回流温度（摄氏度）：NOT SPECIFIED
子类别：Arithmetic Circuit处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

SN74AS866ADW 数据手册

 浏览型号SN74AS866ADW的Datasheet PDF文件第2页浏览型号SN74AS866ADW的Datasheet PDF文件第3页浏览型号SN74AS866ADW的Datasheet PDF文件第4页浏览型号SN74AS866ADW的Datasheet PDF文件第5页浏览型号SN74AS866ADW的Datasheet PDF文件第6页浏览型号SN74AS866ADW的Datasheet PDF文件第7页 
SN54AS866, SN74AS866A  
8-BIT MAGNITUDE COMPARATORS  
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990  
SN54AS866 . . . JD PACKAGE  
SN74AS866A . . . N PACKAGE  
(TOP VIEW)  
• Package Options Include Plastic Small  
Outline Packages, Both Plastic and Ceramic  
Chip Carriers, and Standard Plastic and  
Ceramic DIPs  
QLE  
L/A  
V
CC  
1
28  
27  
26  
25  
24  
• Input and Output Latches with Active-High  
CLRQ  
PLE  
P7  
2
Enables  
p < Qin  
P > Qin  
Q7  
3
• Fast Compare to Zero  
• Arithmetic and Logical Comparison  
• Open-Collector P = Q Output  
4
P6  
5
Q6  
6
23 P5  
7
22  
21  
20  
19  
18  
17  
16  
15  
Q5  
P4  
8
Q4  
P3  
description  
9
Q3  
P2  
10  
11  
12  
13  
14  
These Advanced Schottky devices are capable of  
performing high-speed arithmetic or logical  
comparisons on two 8-bit binary or two’s  
complement words. Three fully decoded  
decisions about words P and Q are externally  
available at the outputs. These devices are fully  
expandable to any word length by connecting the  
totem pole P>Q and P<Q outputs of each stage to  
the P>Q and P<Q inputs of the next higher-order  
stage. The cascading paths are implemented with  
only a two-gate-level delay to reduce overall  
comparison times for long words. The open-  
collector P=Q output may be wire-ANDed  
together.  
Q2  
P1  
Q1  
P0  
Q0  
P < Qout  
P > Qout  
OLE  
P = Qout  
GND  
SN54AS866 . . . FK PACKAGE  
SN74AS866A . . . FN PACKAGE  
(TOP VIEW)  
4
3
2 1 28 27 26  
5
25 P7  
Q7  
Q6  
Q5  
Q4  
Q3  
Q2  
Q1  
Both input words P and Q plus all three outputs  
(P>Q, P<Q, and P = Q) are equipped with latches  
to provide the designer with temporary data  
storage for avoiding race conditions. The enable  
circuitry is implemented with minimal delay times  
to enhance performance when the devices are  
cascaded for longer word lengths. Each latch is  
transparent when the appropriate latch enable,  
PLE, QLE, or OLE is high.  
6
P6  
P5  
P4  
P3  
P2  
P1  
24  
23  
22  
21  
20  
19  
7
8
9
10  
11  
12 13 14 15 16 17 18  
The enable inputs PLE and QLE and data inputs  
P and Q utilize pnp input transistors to reduce the  
low-level input current requirement to typically  
–0.25 mA, which minimizes loading effects.  
The Q register may be cleared to zero for a fast comparison of the P word to zero.  
The SN54AS866 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74AS866A is characterized for operation from 0°C to 70°C.  
Copyright 1990, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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