5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 触发器/锁存器> SN74AS109AN
SN74AS109AN PDF预览

SN74AS109AN

更新时间： 2024-09-30 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
9页 137K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

阅读下载

中文翻译

获取价格

SN74AS109AN 数据手册

 浏览型号SN74AS109AN的Datasheet PDF文件第2页浏览型号SN74AS109AN的Datasheet PDF文件第3页浏览型号SN74AS109AN的Datasheet PDF文件第4页浏览型号SN74AS109AN的Datasheet PDF文件第5页浏览型号SN74AS109AN的Datasheet PDF文件第6页浏览型号SN74AS109AN的Datasheet PDF文件第7页 
SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A  
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SDAS198B – APRIL 1982 – REVISED AUGUST 1995  
SN54ALS109A, SN54AS109A . . . J PACKAGE  
SN74ALS109A, SN74AS109A . . . D OR N PACKAGE  
• Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
(TOP VIEW)  
1CLR  
1J  
V
CC  
2CLR  
2J  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
TYPICAL MAXIMUM TYPICAL POWER  
1K  
CLOCK  
FREQUENCY  
(MHz)  
DISSIPATION  
PER FLIP-FLOP  
(mW)  
TYPE  
1CLK  
1PRE  
1Q  
2K  
2CLK  
′ALS109A  
′AS109A  
50  
6
11 2PRE  
129  
29  
10  
9
1Q  
2Q  
2Q  
GND  
description  
These devices contain two independent J-K  
positive-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the J and K inputs meeting the  
setup-time requirements are transferred to the  
outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a voltage  
level and is not directly related to the rise time of  
the clock pulse. Following the hold-time interval,  
data at the J and K inputs can be changed without  
affecting the levels at the outputs. These versatile  
flip-flops can perform as toggle flip-flops by  
grounding K and tying J high. They also can  
perform as D-type flip-flops if J and K are tied  
together.  
SN54ALS109A, SN54AS109A . . . FK PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18  
1K  
1CLK  
NC  
4
5
6
7
8
2J  
17  
16  
15  
14  
2K  
NC  
1PRE  
1Q  
2CLK  
2PRE  
9 10 11 12 13  
NC – No internal connection  
The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range  
of –55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
H
†
H
L
L
X
H
H
↑
L
H
H
H
↑
H
L
L
Toggle  
H
H
↑
H
H
X
Q0  
H
Q0  
L
H
H
↑
H
X
H
H
L
Q0  
Q0  
†
The output levels in this configuration are not specified to  
meet the minimum levels for V if the lows at PRE and  
OH  
maximum. Furthermore, this  
CLR are near  
V
IL  
configuration is nonstable; that is, it does not persist when  
either PRE or CLR returns to its inactive (high) level.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

SN74AS109AN 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS109AD TI

完全替代

 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS174N TI

功能相似

 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN74AS109ANSR TI

功能相似

 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与SN74AS109AN相关器件

型号 品牌 获取价格 描述 数据表
SN74AS109ANE4 TI

获取价格

 		AS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, RO
SN74AS109ANSR TI

获取价格

 		DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS109ANSRE4 TI

获取价格

 		AS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GR
SN74AS109ANSRG4 TI

获取价格

 		AS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GR
SN74AS109D TI

获取价格

 		暂无描述
SN74AS109DR TI

获取价格

 		Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
SN74AS109J TI

获取价格

 		IC,FLIP-FLOP,DUAL,J/K TYPE,AS-TTL,DIP,16PIN,CERAMIC
SN74AS109N TI

获取价格

 		Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
SN74AS10D TI

获取价格

 		TRIPLE 3-INPUT POSITIVE-NAND GATES
SN74AS10DE4 TI

获取价格

 		TRIPLE 3-INPUT POSITIVE-NAND GATES

与SN74AS109AN相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证