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SN74ALS74ADR PDF预览

SN74ALS74ADR

更新时间: 2024-02-20 13:57:03
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
18页 562K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN74ALS74ADR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:1.25系列:ALS
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:10.3 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:34000000 Hz
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):4 mAProp。Delay @ Nom-Sup:18 ns
传播延迟(tpd):18 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.3 mm最小 fmax:34 MHz
Base Number Matches:1

SN74ALS74ADR 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢃ ꢄꢇ ꢈ ꢀꢁꢂ ꢃ ꢄꢀꢆ ꢃ ꢄ ꢇꢈꢀ ꢁꢆ ꢃ ꢄꢅ ꢀꢆ ꢃ ꢄ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢀ ꢆꢃꢄ  
ꢉ ꢊꢄꢅꢈꢋ ꢌ ꢀꢍꢎ ꢍꢏ ꢐꢑꢐꢉ ꢒꢐ ꢑꢎ ꢓꢍꢒ ꢒ ꢐꢓꢐ ꢉꢈꢉ ꢑꢎ ꢔꢋꢐ ꢈꢕ ꢅꢍ ꢋ ꢑ ꢕꢅꢌ ꢋ ꢀ  
ꢖ ꢍꢎ ꢗꢈ ꢘꢅꢐ ꢄꢓꢈꢄꢁꢉꢈ ꢋ ꢓꢐ ꢀ ꢐꢎ  
SDAS143C − APRIL 1982 − REVISED AUGUST 1995  
SN54ALS74A, SN54AS74A . . . J PACKAGE  
SN74ALS74A, SN74AS74A . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1CLR  
1D  
1CLK  
1PRE  
1Q  
V
CC  
2CLR  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
TYPICAL MAXIMUM  
CLOCK FREQUENCY  
TYPICAL POWER  
2D  
DISSIPATION  
PER FLIP-FLOP  
(mW)  
TYPE  
2CLK  
2PRE  
2Q  
(C = 50 pF)  
L
(MHz)  
50  
1Q  
GND  
ALS74A  
AS74A  
6
2Q  
8
134  
26  
description  
SN54ALS74A, SN54AS74A . . . FK PACKAGE  
(TOP VIEW)  
These devices contain two independent  
positive-edge-triggered D-type flip-flops. A low  
level at the preset (PRE) or clear (CLR) inputs sets  
or resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the data (D) input meeting the  
setup-time requirements are transferred to the  
outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a voltage  
level and is not directly related to the rise time of  
CLK. Following the hold-time interval, data at the  
D input can be changed without affecting the  
levels at the outputs.  
3
2
1
20 19  
18  
1CLK  
NC  
2D  
17 NC  
4
5
6
7
8
16  
15  
14  
1PRE  
NC  
2CLK  
NC  
1Q  
2PRE  
9 10 11 12 13  
NC − No internal connection  
The SN54ALS74A and SN54AS74A are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS74A and SN74AS74A are characterized  
for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
The output levels in this configuration are not  
specified to meet the minimum levels for V if the  
OH  
lows at PRE and CLR are near V maximum.  
IL  
Furthermore, this configuration is nonstable; that  
is, it does not persist when PRE or CLR returns to  
its inactive (high) level.  
ꢎꢤ  
Copyright 1995, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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