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SN74ACT533PWRG4 PDF预览

SN74ACT533PWRG4

更新时间： 2024-02-20 04:04:16
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
10页 289K
描述
ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, TSSOP-20

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SN74ACT533PWRG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, TSSOP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.49Is Samacsys：N
系列：ACTJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：5 V
Prop。Delay @ Nom-Sup：11.5 ns传播延迟（tpd）：11.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN74ACT533PWRG4 数据手册

 浏览型号SN74ACT533PWRG4的Datasheet PDF文件第2页浏览型号SN74ACT533PWRG4的Datasheet PDF文件第3页浏览型号SN74ACT533PWRG4的Datasheet PDF文件第4页浏览型号SN74ACT533PWRG4的Datasheet PDF文件第5页浏览型号SN74ACT533PWRG4的Datasheet PDF文件第6页浏览型号SN74ACT533PWRG4的Datasheet PDF文件第7页 
SN54ACT533, SN74ACT533  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCAS553C – NOVEMBER 1995 – REVISED OCTOBER 2002  
SN54ACT533 . . . J OR W PACKAGE  
SN74ACT533 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 11 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
3-State Inverting Outputs Drive Bus Lines  
Directly  
description/ordering information  
The ’ACT533 devices are octal transparent  
D-type latches with 3-state outputs. When the  
latch-enable (LE) input is high, the Q outputs  
follow the complements of the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the inverted levels set up at the D inputs.  
GND  
SN54ACT533 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
3
2 1 20 19  
18  
8D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17 7D  
16  
7Q  
15  
6Q  
14  
6D  
9 10 11 12 13  
OE does not affect the internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT533N  
SN74ACT533N  
Tube  
SN74ACT533DW  
SN74ACT533DWR  
SN74ACT533NSR  
SN74ACT533DBR  
SN74ACT533PWR  
SNJ54ACT533J  
SNJ54ACT533W  
SNJ54ACT533K  
SOIC – DW  
ACT533  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT533  
AD533  
AD533  
SNJ54ACT533J  
SNJ54ACT533W  
SNJ54ACT533FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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与SN74ACT533PWRG4相关器件

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SN74ACT534 TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ACT534DB TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ACT534DBLE TI

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 		Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85
SN74ACT534DBRE4 TI

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 		Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85
SN74ACT534DW TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ACT534DWG4 TI

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 		ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20
SN74ACT534DWR TI

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 		Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
SN74ACT534DWRG4 TI

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 		ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20
SN74ACT534N TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ACT534NE4 TI

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 		Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-PDIP -40 to 85

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