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SN74ABTH32543MPZEP

更新时间： 2024-10-01 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
10页 174K
描述
36-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ABTH32543MPZEP 数据手册

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SN74ABTH32543-EP  
36-BIT REGISTERED BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCBS757 – AUGUST 2002  
Controlled Baseline  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
– One Assembly/Test Site, One Fabrication  
Site  
Significantly Reduces Power Dissipation  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
Extended Temperature Performance of  
–55°C to 125°C  
= 5 V, T = 25°C  
CC A  
High-Impedance State During Power Up  
and Power Down  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Enhanced Product Change Notification  
†
Qualification Pedigree  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Member of the Texas Instruments  
Widebus+ Family  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
100-Pin Plastic Thin Quad Flat (PZ)  
Package With 14- × 14-mm Body Using  
0.5-mm Lead Pitch  
description  
The’ABTH32543isa36-bitregisteredtransceiverthatcontainstwosetsofD-typelatchesfortemporarystorage  
of data flowing in either direction. This device can be used as two 18-bit transceivers or one 36-bit transceiver.  
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register to permit independent control in either direction of data flow.  
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and  
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches  
inthestoragemode. WithCEABandOEABbothlow, the3-stateBoutputsareactiveandreflectthedatapresent  
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and  
OEBA inputs.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
–55°C to 125°C  
LQFP – PZ  
SN74ABTH32543MPZEP  
74ABTH32543MEP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB  
design guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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SN74ABTH32543MPZEP 替代型号

型号 品牌 替代类型 描述 数据表
5962-9557801NXD TI

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 具有三态输出的 36 位寄存总线收发器 | PZ | 100 | -40 to 85
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