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SN54LS280 PDF预览

SN54LS280

更新时间: 2024-10-01 23:03:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
4页 167K
描述
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

SN54LS280 数据手册

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SN54/74LS280  
9-BIT ODD/EVEN PARITY  
GENERATORS/CHECKERS  
The SN54/74LS280 is a Universal 9-Bit Parity Generator/Checker. It fea-  
tures odd/even outputs to facilitate either odd or even parity. By cascading,  
the word length is easily expanded.  
The LS280 is designed without the expander input implementation, but the  
correspondingfunction is provided by an input at Pin 4 and the absence of any  
connection at Pin 3. This design permits the LS280 to be substituted for the  
LS180 which results in improved performance. The LS280 has buffered  
inputs to lower the drive requirements to one LS unit load.  
9-BIT ODD/EVEN PARITY  
GENERATORS/CHECKERS  
LOW POWER SCHOTTKY  
Generates Either Odd or Even Parity for Nine Data Lines  
Typical Data-to-Output Delay of only 33 ns  
Cascadable for n-Bits  
Can Be Used To Upgrade Systems Using MSI Parity Circuits  
Typical Power Dissipation = 80 mW  
J SUFFIX  
CERAMIC  
CASE 632-08  
14  
1
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
1
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
OUTPUTS  
ORDERING INFORMATION  
FUNCTION TABLE  
SN54LSXXXJ  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
Ceramic  
OUTPUTS  
NUMBER OF INPUTS A  
THRU 1 THAT ARE HIGH  
EVEN ODD  
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
H
L
L
H
H = HIGH Level, L = LOW Level  
GUARANTEED OPERATING RANGES  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
V
CC  
Supply Voltage  
54  
74  
4.5  
4.75  
5.0  
5.0  
5.5  
5.25  
V
T
A
Operating Ambient Temperature Range  
54  
74  
55  
0
25  
25  
125  
70  
°C  
I
I
Output Current — High  
Output Current — Low  
54, 74  
0.4  
mA  
mA  
OH  
54  
74  
4.0  
8.0  
OL  
FAST AND LS TTL DATA  
5-456  

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