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SN54ALS373A_16

更新时间: 2024-10-03 02:58:23
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德州仪器 - TI /
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20页 591K
描述
OCTAL TRANSPARENT D-TYPE LATCHES

SN54ALS373A_16 数据手册

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SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SDAS083C – APRIL 1982 – REVISED MARCH 2002  
SN54ALS373A, . . . J OR W PACKAGE  
SN54AS373 . . . J PACKAGE  
SN74ALS373A, SN74AS373 . . . DW, N, OR NS PACKAGE  
(TOP VIEW)  
Eight Latches in a Single Package  
3-State Bus-Driving True Outputs  
Full Parallel Access for Loading  
Buffered Control Inputs  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
pnp Inputs Reduce dc Loading on Data  
Lines  
8Q  
8D  
7D  
7Q  
6Q  
6D  
description  
These octal transparent D-type latches feature  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
13 5D  
12 5Q  
11  
GND  
LE  
SN54ALS373A, SN54AS373 . . . FK PACKAGE  
(TOP VIEW)  
While the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or a high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and the increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are off.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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