Datasheet > SMM151_10

SMM151_10

更新时间： 2022-05-07 01:33:22

品牌	Logo	应用领域
SUMMIT		/
页数	文件大小	规格书
24页	288K
描述
Single-channel Voltage/Current Monitors and Voltage Marginers

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SMM151_10 数据手册

SMM151/152

PIN DESCRIPTIONS

Number

Type

Pin Name

Pin Description

I/O

SDA

SCL

I²C Bi-directional data line

I²C clock input.

The address pins are biased either to VDD, GND or left floating. This allows

for a total of 21 distinct device addresses. When communicating with the

SMM151/2 over the 2-wire bus these pins provide a mechanism for

assigning a unique bus address.

I/O

GPIO0,1,2,3 SMM152: General purpose inputs/outputs.

3, 9, 22, 27

SMM151: No Connect.

Programmable Write Protect active high/low input. When asserted, writes to

the configuration registers and general purpose EE are not allowed. The

WP input is internally tied to VDD with a 50KΩ resistor.

10, 13

CAP

CAPM+, -

TRIM

External capacitor inputs used to filter the VM+/VM- inputs, 0.22μF.

Output voltage used to control and/or margin converter voltages. Connect to

the converter trim input.

Voltage monitor input. Connect to the DC-DC converter positive sense line

or its +Vout pin.

Voltage monitor input. Connect to the DC-DC converter negative sense line

or its -Vout pin.

Current monitor input + side. Kelvin connect to the input supply side of the

current sense resistor.

Current monitor input - side. Kelvin connect to the load side of the current

sense resistor.

VM+

VM-

CS+

CS-

Internal reference voltage of 1.25V. Connect to GND through a 0.1uF

capacitor to improve noise immunity.

PWR

VREF

CAPC

VDD

External capacitor input used to filter the CS+/CS- input. Typical value: 1uF.

Power supply of the part.

PWR

VDD_CAP

External capacitor input used to filter the internal VDD supply rail.

Ground of the part. The SMM151/2 ground pin should be connected to the

ground of the device under control or to a star point ground. PCB layout

should take into consideration ground drops.

GND

Margin up command input. Asserted high. The MUP input is internally tied to

VDD with a 50KΩ resistor.

Margin down command input. Asserted high. The MDN input is internally

tied to VDD with a 50KΩ resistor.

MUP

MDN

COMP1 and COMP2 are high impedance inputs, each connected internally

to a comparator and compared against the internally programmable VREF

voltage. Each comparator can be independently programmed to monitor for

UV or OV. The monitor level is set externally with a resistive voltage

divider.

COMP1

COMP2

When either of the COMP1 or COMP2 inputs are in fault the open-drain

FAULT# output will be pulled low. A configuration option exists to disable

the FAULT# output while the device is margining.

FAULT#

Summit Microelectronics, Inc

2131 3.0 1/20/2010

1 2 345 6 7...24

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