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SMJ320C6203_08 PDF预览

SMJ320C6203_08

更新时间: 2024-02-24 11:34:00
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
82页 1159K
描述
FIXED-POINT DIGITAL SIGNAL PORCESSOR

SMJ320C6203_08 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢄꢅ ꢃ  
ꢈ ꢉꢊ ꢋꢌꢍꢎꢏ ꢉ ꢐꢑ ꢌꢉ ꢒꢉ ꢑꢓꢔ ꢀꢉ ꢒ ꢐꢓꢔ ꢎꢕ ꢏ ꢆꢋ ꢀ ꢀꢏ ꢕ  
SGUS033 − FEBRUARY 2002  
D
High-Performance Fixed-Point Digital  
Signal Processor (DSP) − SMJ320C62x  
− 5-ns Instruction Cycle Time  
− 200-MHz Clock Rate  
− Eight 32-Bit Instructions/Cycle  
− 1600 Million Instructions Per Second  
(MIPS)  
D
32-Bit External Memory Interface (EMIF)  
− Glueless Interface to Synchronous  
Memories: SDRAM or SBSRAM  
− Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
− 52M-Byte Addressable External Memory  
Space  
D
D
429-Pin Ball Grid Array (BGA) Package  
(GLP Suffix)  
D
D
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
With an Auxiliary Channel  
VelociTIAdvanced Very-Long-Instruction-  
Word (VLIW) C62xDSP Core  
− Eight Highly Independent Functional  
Units:  
32-Bit Expansion Bus  
− Glueless/Low-Glue Interface to Popular  
PCI Bridge Chips  
− Six Arithmetic Logic Units (ALUs)  
(32-/40-Bit)  
− Two 16-Bit Multipliers (32-Bit Result)  
− Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
− Glueless/Low-Glue Interface to Popular  
Synchronous or Asynchronous  
Microprocessor Buses  
− Master/Slave Functionality  
− Glueless Interface to Synchronous FIFOs  
and Asynchronous Peripherals  
− Instruction Packing Reduces Code Size  
− All Instructions Conditional  
D
Three Multichannel Buffered Serial Ports  
(McBSPs)  
− Direct Interface to T1/E1, MVIP, SCSA  
Framers  
− ST-Bus-Switching Compatible  
− Up to 256 Channels Each  
− AC97-Compatible  
D
D
D
Instruction Set Features  
− Byte-Addressable (8-, 16-, 32-Bit Data)  
− 8-Bit Overflow Protection  
− Saturation  
− Bit-Field Extract, Set, Clear  
− Bit-Counting  
− Normalization  
− Serial-Peripheral Interface (SPI)  
Compatible (Motorola)  
Two 32-Bit General-Purpose Timers  
7M-Bit On-Chip SRAM  
− 3M-Bit Internal Program/Cache  
(96K 32-Bit Instructions)  
− 4M-Bit Dual-Access Internal Data  
(512K Bytes)  
D
D
D
D
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
0.15-µm/5-Level Metal Process  
− CMOS Technology  
− Organized as Two 256K-Byte Blocks  
for Improved Concurrency  
3.3-V I/Os, 1.5-V Internal  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SMJ320C62x, VelociTI, and C62x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2002, Texas Instruments Incorporated  
ꢏ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢁꢉ ꢔꢍ ꢎꢕ ꢈ ꢍꢃꢭꢮ ꢃꢮꢯ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢏ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢯ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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