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SMH4802_09 PDF预览

SMH4802_09

更新时间: 2022-03-25 08:54:09
品牌 Logo 应用领域
SUMMIT 控制器
页数 文件大小 规格书
19页 631K
描述
Programmable -48V Hot-Swap Controller with Forced Shut Down

SMH4802_09 数据手册

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SMH4802  
Preliminary Information  
GENERAL DESCRIPTION  
The SMH4802 is an integrated power controller for hot components. Duringthecontrolledturn-onperiodtheVDS  
swappableadd-incards. Thedeviceoperatesfromawide of the MOSFET is monitored by the DRAIN SENSE input.  
supply range and generates the signals necessary to When DRAIN SENSE drops below 2.5V, and VGATE is  
greater than VDD – VGT, the PG# output can begin turning  
drive an isolated output DC/DC converter. As a typical  
add-in board is inserted into the powered backplane, on the DC/DC converter.  
physical connections must first be made with the chassis  
Steady state operation is maintained as long as all  
to discharge any electrostatic voltage potentials. The  
board then contacts the long pins on the backplane that  
provide power and ground. As soon as power is applied,  
the device starts up, but does not immediately apply  
powertotheoutputload. Under-voltageandover-voltage  
circuits inside the controller verify the input voltage is  
within the user-specified range.  
conditions are normal. Any of the following events may  
cause the device to disable the DC/DC controller by  
shutting down the power MOSFET: an under-voltage or  
over-voltage condition on the host power supply; an over-  
current event detected on the CBSENSE input; a failure  
ofthepowerMOSFETsensedviatheDRAINSENSEpin;  
the master enable (EN/TS) falling below 2.5V; or the FS#  
input being driven low by events on the secondary side of  
the DC/DC controller. If one of these events occurs the  
SMH4802 can be configured so VGATE shuts off and  
either latches into an off state or recycles power after a  
Oncetheserequirementsaremet, thehot-swapcontroller  
enables VGATE to turn on the external power MOSFET.  
TheVGATEoutputiscurrentlimitedtoIVGATE, allowingthe  
slew rate to be easily modified using external passive  
cooling down period, tCYC  
.
FUNCTIONAL BLOCK DIAGRAM  
12VREF  
14  
VDD  
PROGRAMMABLE  
SHUTDOWN  
TIMER  
10  
11  
FS#  
+
DRAIN  
SENSE  
1
5.0VREF  
200kΩ  
+
3
8
EN/TS  
UV  
PROGRAMM-  
ABLE  
DELAY  
+
Prog.  
Ref.  
12  
PG#  
+
9
7
OV  
PROGRAMM-  
ABLE  
DELAY  
5V  
12V  
2.5V  
OV/UV  
FILTER  
VSS  
VGATE  
SENSE  
50kΩ  
50kΩ  
5
4
SCL  
SDA  
2
I C INTERFACE  
LOGIC  
2
VGATE  
PROGRAMMED  
DELAY  
+
DUTY  
CYCLE  
TIMER  
50mV  
CBSENSE  
6
+
PROGRAMMED  
Quick-Trip  
2062 BD  
Figure 2. Functional Block diagram. Pin numbers reflect SOIC package.  
2
2062 2.4 03/27/09  
SUMMIT MICROELECTRONICS, Inc.  

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