Datasheet > SM8R-67025L-55

SM8R-67025L-55

更新时间： 2024-09-28 04:50:43

品牌	Logo	应用领域
TEMIC		静态存储器
页数	文件大小	规格书
23页	257K
描述
Dual-Port SRAM, 8KX16, 55ns, CMOS, CPGA84, PGA-84

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SM8R-67025L-55 数据手册

MATRA MHS

M 67025

8 K × 16 CMOS Dual Port RAM

Introduction

The M 67025 is a very low power CMOS dual port static Using an array of eigh transistors (8T) memory cell and

RAM organised as 8192 × 16. The M 67025 is designed fabricated with the state of the art 0.65 µ lithography

to be used as a stand-alone 16 bit dual port RAM or as a named SCMOS, the M 67025 combines an extremely low

combination MASTER/SLAVE dual port for 32 bit or standby supply current (typ = 1.0 µA) with a fast access

width

systems.

The

MATRA-MHS time at 20 ns over the full temperature range. All versions

MASTER/SLAVE dual port approach in memory system offer battery backup data retention capability with a

applications results in full speed, error free operation typical power consumption at less than 5 µW.

without the need of an additional discrete logic.

For military/space applications that demand superior

Master and slave devices provide two independant ports

with separate control, address and I/O pins that permit

independant, asynchronous access for reads and writes to

any location in the memory. An automatic power down

feature controlled by CS permits the on-chip circuitry of

each port in order to enter a very low stand by power

mode.

levels of performance and reliability the M 67025 is

processed according to the methods of the latest revision

of the MIL STD 883 (class B or S) and/or ESA SCC 9000.

Features

D Fast access time : 20/25/30/35/45/55 ns

D Wide temperature range :

D Versatile pin select for master or slave :

– M/S = H for busy output flag on master

– M/S = L for busy input flag on slave

–55 °C to +125 °C

D 67025 L low power

D INT flag for port to port communication

D Full hardware support of semaphore signaling between ports

D Fully asynchronous operation from either port

D Battery back-up operation : 2 V data retention

D TTL compatible

67025 V very low power

D Separate upper byte and lower byte control for multiplexed

bus compatibility

D Expandable data bus to 32 bits or more using master/slave

chip select when using more than one device

D On chip arbitration logic

D Single 5 V ± 10 % power supply

D For 3.3 V version, please consult sales

Rev. D (29/09/95)

12 3 4 5 6 7...23

中文翻译

下载PDF

与SM8R-67025L-55相关器件

型号	品牌	获取价格	描述	数据表
SM8R-67025L-55/883	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 55ns, CMOS, CPGA84, PGA-84
SM8R-67025V-30	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 30ns, CMOS, CPGA84, PGA-84
SM8R-67025V-30/883	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 30ns, CMOS, CPGA84, PGA-84
SM8R-67025V-35/883	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 35ns, CMOS, CPGA84, PGA-84
SM8R-67025V-55/883	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 55ns, CMOS, CPGA84, PGA-84
SM8S	VISHAY	获取价格	Surface Mount Automotive Transient Voltage Suppressors
SM8S	dowosemi	获取价格	表面贴装汽车瞬态电压抑制器 Surface Mount Automotive Trans
SM8S10	VISHAY	获取价格	Surface Mount Automotive Transient Voltage Suppressors
SM8S10	LGE	获取价格	暂无描述
SM8S10	UNSEMI	获取价格