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SM12808DT-6.6 PDF预览

SM12808DT-6.6

更新时间: 2024-01-07 01:21:13
品牌 Logo 应用领域
铁电 - RAMTRON 动态存储器内存集成电路
页数 文件大小 规格书
12页 153K
描述
Synchronous DRAM Module, 32MX64, 4.5ns, CMOS, DIMM-168

SM12808DT-6.6 技术参数

是否无铅: 含铅生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM,
针数:168Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.75访问模式:DUAL BANK PAGE BURST
最长访问时间:4.5 ns其他特性:AUTO/SELF REFRESH
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:2147483648 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:168
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY认证状态:Not Qualified
刷新周期:4096自我刷新:YES
子类别:DRAMs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:DUALBase Number Matches:1

SM12808DT-6.6 数据手册

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CAS2/150MHz HSDRAM  
64MB, 128MB DIMM  
Preliminary Data Sheet  
Pin Descriptions  
Symbol  
CK0,1,2,3  
CKE0,1  
Type  
Input  
Input  
Function  
Clocks: All SDRAM input signals are sampled on the positive edge of CK.  
Clock Enables: CKE activate (high) or deactivate (low) the CK signals. Deactivating the clock initiates the  
Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until  
the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.  
S0,1,2,3#  
Input  
Input  
Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is  
disabled, new commands are ignored but previous operations continue.  
RAS#, CAS#,  
WE#  
Command Inputs: Sampled on the rising edge of CK, these inputs define the command to be executed.  
Bank Addresses: These inputs define to which of the 4 banks a given command is being applied.  
BA1, BA0  
A0-A11  
Input  
Input  
Address Inputs: A0-A11 define the row address during the Bank Activate command. A0-A8 define the column  
address during Read and Write commands. A10/AP invokes the Auto-precharge operation. During manual  
Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.  
The address inputs are also used to program the Mode Register.  
DQ0-DQ63  
Input/  
Output  
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up  
and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after  
the CAS latency is satisfied.  
DQMB0-7  
CB0-7  
Input  
Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable  
(2-cycle latency) for read data.  
Input/  
Output  
Supply  
ECC Check Bits  
VDD  
VSS  
Power Supply: +3.3 V  
Ground  
Supply  
SDA  
Input/  
Output  
Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into  
and data out of the presence-detect portion of the module.  
SCL  
Input  
Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to  
and from the module  
SA0-2  
WP  
Input  
Input  
Presence-Detect Address Inputs: These pins are used to configure the presence detect device.  
Serial Presence Detect Write Protect: Active high inhibits writes to the SPD EEPROM. WP must be driven low  
for normal read/write operations.  
RFU  
DNU  
NC  
-
-
-
Reserved for Future Use: These pins should be left unconnected.  
Do not use.  
No connect - open pin.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
2000 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Page 2 of 12  
Revision 1.0  

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