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SL18860 PDF预览

SL18860

更新时间: 2024-01-02 08:31:11
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
12页 269K
描述
3-Channel Clock Distribution Buffer

SL18860 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DFN包装说明:TDFN-10
针数:10Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:8.57Is Samacsys:N
其他特性:IT ALSO OPERATED WITH 2.5 AND 3.3 V SUPPLYJESD-30 代码:R-PDSO-N10
长度:2 mm端子数量:10
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:52 MHz封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:52 MHz认证状态:Not Qualified
座面最大高度:0.8 mm最大供电电压:1.9 V
最小供电电压:1.7 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.4 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

SL18860 数据手册

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SL18860DC  
3-Channel Clock Distribution Buffer  
Key Features  
Description  
The SL18860DC product is a high performance 3 output  
clock distribution buffer and provides 3 outputs from a  
single input clock by using SLI proprietary low phase  
noise and low power dissipation circuit design.  
Low current consumption  
- 2.7mA-typ (VDD=1.8V and CL=0)  
1.7V to 3.65V power supply operation  
10MHz to 52MHz CLKIN  
Supports LVCMOS and clipped sine wave inputs  
Suports 3 single-ended LVCMOS square wave  
outputs  
OE1/2/3 functions for each CLKOUT1/2/3 outputs  
OE_OSC control pin to enable external TCXO/XO  
Ultra-Low phase noise  
The SL18860DC can be used in baseband mobile RF  
applications including WLAN, Bluetooth and DVB-H as an  
input clock reference. The product designed to isolate  
each device driven by their clock outputs to minimize  
interference between these devices.  
Each of the clock buffer outputs can be individually  
disabled by using OE1/2/3 control pins to reduce the  
power consumption if the connected device does not need  
the clock. The device operates from single power supply  
from 1.7V to 3.65V and from -40 ºC to 85 ºC.  
Ultra low standby current  
10-pin TDFN package (1.4x2.0x0.75 mm)  
Industrial -40 ºC to 85 ºC temperature range  
Application  
Benefits  
Fast Time-to-market  
Cost Reduction  
Low Power Dissipation  
Low Phase Noise  
Smart Mobile Handsets  
Multi-mode RF Clock Distribution  
Baseband Peripheral Clock Distribution  
Block Diagram  
8
CLKOUT1  
3
9
CLKOUT2  
CLKIN  
4
OE_OSC  
10 CLKOUT3  
CONTROL LOGIC  
6
7
5
2
1
OE1  
OE2  
OE3  
VDD  
VSS  
Rev 1.8, March 16 , 2012  
400 West Cesar Chavez, Austin, TX 78701  
Page 1 of 12  
1+(512) 416-8500  
1+(512) 416-9669  
www.silabs.com  

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