DATA SHEET
APRIL 2000
Revision2.0
SK70725A/SK70721
Enhanced Multi-Rate DSL Data Pump Chip Set
General Description
Features
The Enhanced Multi-Rate DSL Data Pump (EMDP) is a
variable-rate transceiver that provides symmetric full-
duplex communication on one twisted wire pair using a
2B1Q line code with echo-cancellation. The EMDP
operates in either framed or Transparent modes and
supports channelized, cell and packet applications.
Symmetrical line rates may be at any speed between 272
and 1,168 kbps. Performance is specified at 272, 400, 528
784 and 1,168 kbps for payloads of 4, 6, 8, 12 or 18
channels at 64 kbps and 16 kbps of overhead. The EMDP
chip set consists of two devices:
• Fully integrated, 2-chip transceiver. Compliant with
the following standards:
• ITU G.991.1
• ANSI Committee T1E1.4-TR28 (T1E1.4/96-006)
• ETSI ETR-152
• Integrated line drivers, filters and hybrid circuits
reduce the number of external components required
• Multiple framing modes: Transparent, T1 standard,
E1 standard
• Independent transmit and receive clocks for minimum
delay
• Tolerance for extended signal interruptions
• Single +5V supply
• SK70725A-EnhancedDigitalSignalProcessor(EDSP)
• SK70721- Integrated Analog Front-End (IAFE)
• Supports processor directed rate selection driven by
The IAFE is a fully integrated CMOS analog front-end
which includes D/A converter, filters, and transmit line
drivers. Receiver functions include analog echo canceller,
AGC, A/D converter modulator and VCXO functions. The
EDSP incorporates all digital signal processing required
for A/D conversion, echo-cancellation, data scrambling
and adaptive equalization as well as transceiver activation
state machine control.
receive signal level and noise margin
• Continuously adaptive echo canceller and equalizers
maintain excellent transmission performance with
changing noise and line characteristics
• Typical noise-free transmission range:
• 272 kbps
25.3 kft (7.7 km) on 24 AWG (0.5 mm) wire
17.1 kft (5.2 km) on 26 AWG (0.4 mm) wire
• 784 kbps
Applications
19.8 kft (6.0 km) on 24 AWG (0.5 mm) wire
• High speed symmetrical Internet access
• Extended range fractional T1/E1 transport
• Digital pairgain systems from 4 to 18 channels
• Wireless base station access
13.7 kft (4.2 km) on 26 AWG (0.4 mm) wire
• 1,168 kbps
17.1 kft (5.2 km) on 24 AWG (0.5 mm) wire
12.3 kft (3.7 km) on 26 AWG (0.4 mm) wire
• WAN access for 10BaseT and ATM LANs
• Video Conferencing Systems
SK70725A/SK70721
Block Diagram
IAFE
EDSP
TX_CLK
Line
MASTER_CLK
E
n
Driver
Tx
c
TTIP
Data
o
Fltr
DATA
AND
Select
Framer
2B1Q
TSGN
TMAG
d
e
r
Encoder
Scrambler
TRING
CLOCK
Activation
Control
Logic
Echo
Control
VREF
Canceller
MODE
DFE
CONTROL
FFE
DAGC
AGC
Tap
Deci
mator
Decision
Circuit
AD0
AD1
Back
End
Σ
RTIP
BRING
RRING
Σ
STATUS
Σ
INDICATORS
AGC
Logic
Σ
AGC_SET
VCO_CLK
BTIP
Phase
Detector
µ
I/F
P
XI
XO
VPLL
VCO
Serial
I/F
To Various
Blocks
SRCTL_FS
SER_CTL
Refer to www.level1.com for most current information.
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