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SK70744HE PDF预览

SK70744HE

更新时间： 2024-09-28 20:08:51
品牌 Logo 应用领域
英特尔 - INTEL 电信电信集成电路
页数 文件大小 规格书
80页 441K
描述
Framer, CMOS, PQFP100, MO-112, QFP-100

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中文翻译

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SK70744HE 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：QFP, QFP100,.7X.9针数：100
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：8.81数据速率：1500 Mbps
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm功能数量：1
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.7X.9
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5,3.3 V
认证状态：Not Qualified座面最大高度：3.1 mm
子类别：Other Telecom ICs标称供电电压：2.5 V
表面贴装：YES技术：CMOS
电信集成电路类型：FRAMER温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

SK70744HE 数据手册

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SK70740/44  
HDSL2 Modem Chip Set  
Datasheet  
The SK70740 and SK70744 chip set provide full-duplex, T1 (DS-1) transmission over a single  
twisted pair. The chip set is capable of providing Overlapped PAM Transmission with  
Interlocking Spectra (OPTIS) power spectral density (PSD). The chip set consists of two ICs that  
provide the HDSL2 modem solution:  
■ SK70740HE - Analog Front End (AFE)  
■ SK70744HE - Transceiver/Framer  
The SK70740 AFE is separated into a transmit and receive channel. In the transmit channel, the  
AFE receives a pulse width modulated data stream from the digital transceiver. Switched  
capacitor filters shape the transmitted signal to suppress out-of-band noise. The receive channel  
consists of an automatic gain control (AGC) stage and an analog to digital (A/D) converter. The  
dynamic range of the receive channel is over 80 dB.  
The core of the SK70744 Transceiver/Framer is a Trellis Coded PAM modulator/demodulator.  
HDSL2 utilizes shaped PAM-16 modulation to minimize interference into other services. The  
transmit filter can be programmed through firmware, allowing the transmit power spectrum to be  
optimized for the regional conditions. In addition, Trellis Coding (TC) and Viterbi Decoding,  
allows the system to provide high signal to noise margin in the presence of crosstalk noise from  
other services.  
The frame mapping function inserts and recovers the HDSL2 overhead. Interrupt alarms are  
provided for loss of sync and CRC errors. The system also has read/write register access to the  
Embedded Operations Channel (EOC) bits within the HDSL2 frame. A synchronous data  
interface allows use with common T1 framers.  
Applications  
■ T1 transport systems  
■ Multi-channel digital pair gain systems  
■ WAN access for LAN routers and switches  
■ Integrated access devices  
■ Wireless access systems  
Product Features  
■ Supports ANSI T1E1.418 (HDSL2)  
■ I/O operates at 3.3 V logic levels and is 5V  
specification  
tolerant  
■ Programmable for either Central Office  
(H2TU-C) or Remote (H2TU-R)  
applications  
■ Intel/Motorola compatible 8-bit  
microprocessor interface allows rapid  
setup, acquisition and status monitoring  
■ Operates from a single crystal reference  
■ Programmable activation controller  
minimizes load on the system processor  
■ High resolution, Delta-Sigma A/D  
converter  
■ Internal circuitry for wander reduction  
As of January 15, 2001, this document replaces the Level One document  
SK70740/44 HDSL2 Modem Chip Set Datasheet.  
Order Number: 249345-001  
January 2001  
1234567...80

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