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SG-AA3TCE2-FREQ PDF预览

SG-AA3TCE2-FREQ

更新时间: 2022-12-20 00:59:30
品牌 Logo 应用领域
其他 - ETC 石英晶振压控振荡器有源晶体振荡电路
页数 文件大小 规格书
3页 163K
描述
HF/UHF SMD TCVCXO

SG-AA3TCE2-FREQ 数据手册

 浏览型号SG-AA3TCE2-FREQ的Datasheet PDF文件第1页浏览型号SG-AA3TCE2-FREQ的Datasheet PDF文件第3页 
Data Sheet 0631B  
CRYSTAL CLOCK OSCILLATORS  
Rev. A  
SG-XA3XXXX Series Continued  
HF/UHF SMD TCVCXO  
Absolute Maximum Ratings  
Parameter  
Input Break Down Voltage  
Storage Temperature  
Control Voltage  
Sym  
Condition  
Min  
-0.5  
-40  
-1  
Typ  
Max  
5.5  
105  
9
Unit  
V
Note  
Note  
Vcc  
Ts  
ºC  
V
Vc  
Electrical Parameters  
Parameter  
Sym  
Conditions  
MIN  
30  
TYP  
MAX  
200  
Unit  
Frequency Range  
F
CMOS  
MHz  
Sine-wave  
30  
1,000  
1,000  
5.25  
3.465  
30  
PECL,LVDS  
Code 0  
30  
4.75  
3.135  
Input Voltage  
Input current  
Vcc  
Icc  
5.0  
3.3  
V
Code A  
CMOS,Sine  
PECL, Sine,LVDS  
Overall, available  
vs Temperature  
vs Vcc  
mA  
@100MHz, 3.3V  
@622MHz, 3.3V  
20 years  
100  
±4.6  
±1  
Frequency Stability  
Frequency Stability  
F/F  
F/F  
±0.5  
±0.1  
±1  
ppm  
ppm/V  
ppm/year  
ppm  
See Chart  
Aging  
First Year  
10 years  
±3.5  
±0.5  
Calibration  
Load  
F/F  
As shipped, 25°C  
CMOS  
±1  
ppm  
15pf/10KOhmOhm  
Sinewave  
PECL  
Internally AC-coupled 50 Ohm  
50 Ohm to Vcc-2V or Thevenin equivalent  
100 Ohm between the outputs, receiving end  
LVDS  
Duty Cycle  
Rise/Fall Time  
At 50 %  
45/55  
50/50  
3
55/45  
%
ns  
CMOS, PECL, LVDS  
CMOS  
Tr/Tf  
20 to 80%  
0.35  
PECL, LVDS  
Logic “1" level  
Logic “0" level  
Logic “1" level  
Logic “0" level  
Output Levels  
LVDS  
Voh  
Vol  
Voh  
Vol  
Vod  
CMOS  
0.9Vcc  
V
V
CMOS  
0.1Vcc  
Vcc-0.81  
Vcc-1.65  
454  
PECL  
Vcc-0.96  
Vcc-1.85  
247  
V
100K available  
100K available  
PECL  
V
Differential  
330  
mV  
amplitude  
Amplitude error  
Offset Voltage  
Offset Voltage error  
Sinewave Into 50  
Ohm  
50  
1.375  
50  
mV  
V
Vof  
P
1.125  
4
1.25  
37  
mV  
dBm  
Output power  
3.3V  
5.0V  
Start up Time  
Phase jitter  
Ts  
2
10  
1
ms  
ps  
1 sigma  
0.4  
0.2  
-45  
100Hz to 20MHz  
12kHz to 20MHz  
F>250MHz  
0.4  
-40  
none  
-60  
-25  
Sub-harmonics  
PECL, LVDS, Sine  
CMOS, Sine  
dBc  
F<250MHz  
Spurious  
dBc  
dBc  
dBc/Hz  
Harmonics  
Sine-wave  
@10 Hz  
-30  
-80  
SSB Phase Noise  
@ 100 MHz  
@100 Hz  
@1 KHz  
@10KHz  
@100KHz  
@10 Hz  
-110  
-140  
-155  
-160  
SSB Phase Noise  
-60/-60  
-90/-90  
-120/-120  
-140/-145  
-145/-150  
> 10 K Ohm  
dBc/Hz  
@ 622 Mhz;  
@100 Hz  
@1 KHz  
@10KHz  
@100KHz  
PECL,LVDS/Sine  
Input Impedance  
Control Voltage  
Vc  
MB  
0
3.3  
V
Modulation Bandwidth  
100Hz  
Contact Factory for  
wider MB  
Deviation  
Vc=0V to 3.3V,  
25°C  
±5  
±7  
ppm  
357 Beloit Street, P.O. Box 457, Burlington, WI 53105-0457 U.S.A. Phone 262/763-3591 FAX 262/763-2881  
Email: nelsales@nelfc.com www.nelfc.com  

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