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SCD243110QCD PDF预览

SCD243110QCD

更新时间： 2024-10-03 21:19:43
品牌 Logo 应用领域
英特尔 - INTEL 通信时钟数据传输外围集成电路
页数 文件大小 规格书
186页 979K
描述
Serial I/O Controller, 4 Channel(s), 0.01640625MBps, CMOS, PQFP100, METRIC, QFP-100

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SCD243110QCD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP, QFP100,.7X.9
针数：100Reach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.88
地址总线宽度：16边界扫描：NO
最大时钟频率：35 MHz通信协议：ASYNC, BIT; SYNC, HDLC; ASYNC, HDLC; SYNC, SDLC; PPP; MNP4; SLIP
数据编码/解码方法：NRZ; NRZI; BIPH-LEVEL(MANCHESTER)最大数据传输速率：0.01640625 MBps
外部数据总线宽度：16JESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
低功率模式：NO串行 I/O 数：4
端子数量：100最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.7X.9
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：3.4 mm
子类别：Other Microprocessor ICs最大压摆率：50 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches：1

SCD243110QCD 数据手册

 浏览型号SCD243110QCD的Datasheet PDF文件第2页浏览型号SCD243110QCD的Datasheet PDF文件第3页浏览型号SCD243110QCD的Datasheet PDF文件第4页浏览型号SCD243110QCD的Datasheet PDF文件第5页浏览型号SCD243110QCD的Datasheet PDF文件第6页浏览型号SCD243110QCD的Datasheet PDF文件第7页 
CD2431  
Advanced Multi-Protocol Communications Controller  
Datasheet  
The CD2431 is a 4-channel synchronous/asynchronous communications controller specifically  
designed to reduce host-system processing overhead and increase efficiency in a wide variety of  
communications applications. The CD2431 is packaged in a 100-pin MQFP, and offers eight  
clock/modem pins per channel. The device has four fully independent serial channels that  
support asynchronous, asynchronous-HDLC, and bit-synchronous (HDLC/SDLC) protocols.  
The CD2431 is based on a proprietary on-chip RISC processor that performs all time-critical,  
low-level tasks that are otherwise performed by the host system.  
The CD2431 boosts system efficiency with on-chip DMA, on-chip FIFOs, intelligent vectored  
interrupts, and intelligent protocol processing. The on-chip DMA controller provides ‘fire-and-  
forget’ transmit support — the host need only inform the CD2431 of the location of the packet to  
be sent. Similarly, on receive, the CD2431 automatically receives a complete packet with no host  
intervention or assistance required. The DMA controller also has an ‘Append mode’ for use in  
asynchronous applications.  
The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer  
schemes. Each channel and direction has two active buffers.  
The CD2431 can be programmed to interrupt the host at the completion of a frame or buffer. In  
applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames  
to be divided into multiple buffers.  
For applications where a DMA interface is not desired, the device can be operated as an  
interrupt-driven or polled device. This choice is available individually for each channel and each  
direction. For example, a channel can be programmed for DMA transmit and interrupt-driven  
receive.  
In either case, 16-byte FIFOs on each channel and in each direction reduce latency time  
requirements, making both software and hardware designs less time-critical. Threshold levels on  
FIFOs are user-programmable.  
Efficient vectored interrupts are another way the CD2431 help system efficiency. Separate  
interrupts are generated for transmit, receive, and modem-signal change, with unique user-  
defined vectors for each type and channel. This allows very flexible interfacing and fast,  
efficient interrupt coding. For example, the Good Data interrupt allows the host to vector  
directly to a routine that transfers the data — no status or error checking is required.  
As of May 2001, this document replaces the Basis Communications  
Corp. document CL-CD2431 — Advanced Multi-Protocol Communications Controller.  
May 2001  
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