Preliminary
SC3042B
• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
624.0 MHz
Differential
Sine-Wave
Clock
• Very Low Jitter and Power Consumption
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use in high-speed communications timing systems. Fundamental-mode
oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter,
compact size, and low power consumption. Differential outputs provide a sine wave that is capable of driving
50 Ω loads.
Absolute Maximum Ratings
Rating
Value
0 to +4.0
0 to +4.0
-40 to +85
Units
VDC
VDC
°C
Power Supply Voltage (V at Terminal 1)
CC
Input Voltage (ENABLE at Terminal 8)
Case Temperature (Powered or Storage)
SMC-8 Case
Electrical Characteristics
Characteristic
Sym
Notes
Minimum
Typical
Maximum
Units
Output Frequency
Absolute Frequency
f
623.875
624.125
MHz
O
1, 2
Tolerance from 624.0 MHz
Voltage into 50Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
Δf
±200
1.1
2:1
51
ppm
O
V
0.60
49
Q and Q Output
O
V
1, 3
P-P
3, 4, 5
3, 4, 6
%
Harmonic Spurious
-30
-60
30
dBc
dBc
Nonharmonic Spurious
No Noise on V
3, 4, 6, 7
3, 4, 7, 8
3, 9
15
ps
Q and Q Period Jitter
Output (Disabled)
CC
P-P
200 mV
from 1 MHz to ½ f on
35
ps
P-P
O
P-P
Amplitude into 50 Ω
75
mV
P-P
50
KΩ
V
3
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
V
V
-0.1
V
V
+0.1
IH
CC
CC
CC
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
Operating Voltage
Operating Current
V
I
0.0
0.20
5
V
IL
3
mA
mA
ms
VDC
mA
°C
3, 9
IH
I
-1
IL
t
1
PD
DC Power Supply
V
I
+3.13
0
+3.30
20
+3.47
40
CC
1, 3
1, 3
CC
Operating Ambient Temperature
T
+70
A
Lid Symbolization (YY = Year, WW = Week)
RFM SC3042B 624.00 MHz YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1.
Unless otherwise noted, all specifications include any combination of load
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads
to ground. (See: Typical Test Circuit.)
6.
Jitter and other spurious outputs induced by externally generated electrical
noise on V or mechanical vibration are not included. Dedicated external
CC
voltage regulation and careful PCB layout are recommended for optimum
performance.
2.
3.
4.
5.
One or more of the following United States patents apply: 4,616,197;
4,670,681; 4,760,352.
7.
8.
Applies to period jitter of Q and Q. Measurements are made with the
Tektronix CSA803 signal analyzer with at least 1000 samples.
The design, manufacturing process, and specifications of this device are
subject to change without notice.
Period jitter measured with a 200 mV
sine wave swept from 1 MHz to
P-P
Only under the nominal conditions of 50 Ω load impedance with VSWR ≤
one-half of f at the V power supply terminal.
O
CC
1.2 and nominal power supply voltage.
9.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation
delay is defined as the time from the 50% point on the rising edge of
ENABLE to the 90% point on the rising edge of the output amplitude or as
the fall time from the 50% point to the 10% point. (SEE: Timing
Definitions.)
Symmetry is defined as the pulse width (in percent of total period)
measured at the 50% points of Q or Q. (See: Timing Definitions.)
www.RFM.com
E-mail: info@rfm.com
Page 1 of 2
©2008 by RF Monolithics, Inc.
SC3042B - 3/27/08
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