CCD area image sensor S8667-1010
ꢀ Absolute maximum ratings (Ta=25 °C)
Parameter
Symbol
Topr
Min.
-
Typ.
Max.
+50
+70
+25
+18
+15
+15
+15
+15
+15
+15
+15
Unit
°C
°C
V
Operating temperature
Storage temperature
OD voltage
-
-
-
-
-
-
-
-
-
-
-
Tstg
-
VOD
-0.5
-0.5
-10
-10
-0.5
-10
-10
-10
-10
RD voltage
VRD
V
TG voltage
VTG
V
SG, OG, RG voltage
ISH voltage
VSG, VOG, VRG
VISH
V
V
IGH voltage
VIG1H, VIG2H
VP1VI, VP2VI
VP1VS, VP2VS
VP1H, VP2H
V
Vertical clock voltage (image area)
Vertical clock voltage (storage area)
Horizontal clock voltage
V
V
V
Operating conditions (MPP mode, Ta=25 °C)
Parameter
ꢀ
Symbol
VOD
Min.
12
11.5
1
Typ.
15
12
3
Max.
18
12.5
5
Unit
V
Output transistor drain voltage
Reset drain voltage
VRD
V
Output gate voltage
VOG
V
Substrate voltage
VSS
-
0
-
V
Test point (vertical input source)
Test point (horizontal input source)
Test point (vertical input gate)
Test point (horizontal input gate)
Vertical shift register
VISV
-
VRD
VRD
0
-
V
VISH
-
-
V
VIG1V, VIG2V
VIG1H, VIG2H
VP1VIH, VP2VIH
-8
-8
4
-
V
0
-
V
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
6
8
V
V
V
V
V
V
clock voltage (image area)
V
P1VIL, VP2VIL
-9
4
-8
6
-7
8
VP1VSH, VP2VSH
VP1VSL, VP2VSL
VP1HH, VP2HH
Vertical shift register
clock voltage (storage area)
-9
4
-8
6
-7
8
Horizontal shift register
clock voltage
V
P1HL, VP2HL
VSGH
-9
4
-8
6
-7
8
Summing gate voltage
Reset gate voltage
VSGL
-9
4
-8
6
-7
8
VRGH
VRGL
-9
4
-8
6
-7
8
VTGH
Transfer gate voltage
VTGL
-9
-8
-7
Electrical characteristics (Ta=25 °C)
Parameter
ꢀ
Symbol
fc
Remark
Min.
Typ.
-
Max.
Unit
MHz
MHz
Signal output frequency
Reset clock frequency
-
-
14
14
frg
10
CP1VI, CP2VI
CP1VS, CP2VS
CP1H, CP2H
CSG
Vertical shift register capacitance
-
6,000
-
pF
Horizontal shift register capacitance
Summing gate capacitance
Reset gate capacitance
-
-
-
-
-
120
-
-
-
-
-
pF
pF
pF
pF
-
7
7
CRG
Transfer gate capacitance
Transfer efficiency
CTG
50
1
*
CTE
Vout
Zo
0.99995
2
*
DC output level
7
-
10
13
-
V
W
2
*
Output impedance
Power dissipation
500
100
*2, *3
P
-
-
mW
*1: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*2: VOD=15 V, Load resistance=2.2 kW
*3: Power dissipation of the on-chip amplifier.
2