1 Gbit, 1.8 V Dual-Quad Serial Peripheral Interface with Multi-I/O Flash
Signal description
3.2
Multiple Input / Output (Dual-Quad)
Quad Input / Output (I/O) commands send instructions to the memory only on the IO0 (Quad SPI-1) and IO4 (Quad
SPI-2) signals. Address is sent from the host to the memory as four bit (nibble) on IO0, IO1, IO2, IO3 (Quad
SPI-1)and repeated on IO4, IO5, IO6, IO7 (Quad SPI-2). Data is sent and returned to the host as bytes on IO0–IO7.
3.3
Serial Clock (SCK1, SCK2)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data
input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR
commands, and after every edge in DDR commands.
3.4
Chip Select (CS1#, CS2#)
The Chip Select signal indicates when a command is transferring information to or from the device and the other
signals are relevant for the memory device.
When the CS# signal is at the logic HIGH state, the device is not selected and all input signals are ignored and all
output signals are high impedance. The device will be in the Standby Power mode, unless an internal embedded
operation is in progress. An embedded operation is indicated by the Status Register 1 Write-In-Progress bit
(SR1V[1]) set to ‘1’, until the operation is completed. Some example embedded operations are: Program, Erase,
or Write Registers (WRR) operations.
Driving the CS# input to the logic LOW state enables the device, placing it in the Active Power mode. After
Power-up, a falling edge on CS# is required prior to the start of any command.
3.5
Serial Input (IO0, IO4)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to
be programmed. Values are latched on the rising edge of serial SCK clock signal.
Input and output during Quad commands for receiving instructions, addresses, and data to be programmed
(values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK,
in SDR commands, and on every edge of SCK, in DDR commands).
3.6
Serial Output (IO1, IO5)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the
serial SCK clock signal.
Input and output during Quad commands for receiving addresses, and data to be programmed (values latched
on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR commands,
and on every edge of SCK, in DDR commands).
3.7
Write Protect (WP1#, WP2#) / (IO2, IO6)
When WP# is driven LOW (VIL), during a WRR or WRAR command and while the Status Register Write Disable
(SRWD_NV) bit of Status Register 1 (SR1NV[7]) is set to ‘1’, it is not possible to write to Status Register 1 or
Configuration Register 1 related registers. In this situation, a WRR command is ignored, a WRAR command
selecting SR1NV, SR1V, CR1NV, or CR1V is ignored, and no error is set.
This prevents any alteration of the Block Protection settings. As a consequence, all the data bytes in the memory
area that are protected by the Block Protection feature are also hardware protected against data modification if
WP# is LOW during a WRR or WRAR command with SRWD_NV set to ‘1’.
The WP# function is not available when the Quad mode is enabled (CR1V[1] = 1). The WP# function is replaced by
IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are
latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands,
and on every edge of SCK, in DDR commands).
WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the host
system if not used for Quad mode or protection.
Datasheet
9
002-25385 Rev. *D
2023-04-22
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