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S5T8809 PDF预览

S5T8809

更新时间: 2022-11-26 02:59:57
品牌 Logo 应用领域
三星 - SAMSUNG /
页数 文件大小 规格书
14页 126K
描述
PLL FREQUENCY SYNTHESIZER FOR PAGER

S5T8809 数据手册

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S5T8809  
PLL FREQUENCY SYNTHESIZER FOR PAGE  
RD = R = 5 ~ 32767 [All value]  
CONTROL MODE FOR R-COUNTER REGISTER  
LDC  
LDC Pin State  
Low  
Normal Operation  
Description  
LDC function is independent of the other Control Bit  
0
1
FRC  
R-Counter Value  
Description  
0
1
8 ´ R_cnt value (OSCI / 8 ´ R), FRC function is independent of the other Control Bit  
Use 13 bits R-Counter  
R-cnt value (OSC / R),  
Use 15 bits R-Counter  
TEST1  
TEST  
LD state  
Normal  
FL state  
Normal  
Description  
• FRC is independent of the other control bit  
0
1
0
1
0
0
1
1
• Test is internal register control bit  
but, Test is external control pin  
Normal  
Normal  
Fn (N-CNT)  
Fr (N-CNT)  
High state  
Normal  
• Test is related with Test,  
when Test = High ® Test Mode  
PMC = 1 ® 13/15 bit R-Counter, LDC, FRC, TEST1  
PMC  
R_Counter Divider Data ( RD14 ~ RD0 )  
LDC FRCTEST1  
DATA  
MSB  
LSB  
13 14 15 16 17 18 19  
1
2
3
4
5
6
7
8
CLK  
EN  
MSB : 1st INPUT  
positive edge triggered  
Figure 2. Ref. R-Counter Register Programming Timing  
8

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