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S3C4510B01-QE80 PDF预览

S3C4510B01-QE80

更新时间: 2024-10-01 19:53:31
品牌 Logo 应用领域
三星 - SAMSUNG /
页数 文件大小 规格书
422页 2160K
描述
Micro Peripheral IC, PQFP208,

S3C4510B01-QE80 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QFP, QFP208,1.2SQ,20Reach Compliance Code:compliant
风险等级:5.82JESD-30 代码:S-PQFP-G208
端子数量:208最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP208,1.2SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
子类别:Other Microprocessor ICs最大压摆率:230 mA
标称供电电压:3.3 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
Base Number Matches:1

S3C4510B01-QE80 数据手册

 浏览型号S3C4510B01-QE80的Datasheet PDF文件第2页浏览型号S3C4510B01-QE80的Datasheet PDF文件第3页浏览型号S3C4510B01-QE80的Datasheet PDF文件第4页浏览型号S3C4510B01-QE80的Datasheet PDF文件第5页浏览型号S3C4510B01-QE80的Datasheet PDF文件第6页浏览型号S3C4510B01-QE80的Datasheet PDF文件第7页 
S3C4510B  
PRODUCT OVERVIEW  
1
PRODUCT OVERVIEW  
OVERVIEW  
Samsung's S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller  
solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4510B, is designed for use in  
managed communication hubs and routers.  
The S3C4510B is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by  
Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell  
that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and  
fully static design is particularly suitable for cost-sensitive and power-sensitive applications.  
The S3C4510B offers a configurable 8K-byte unified cache/SRAM and Ethernet controller which reduces total  
system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the  
S3C4510B has been fully verified in Samsung's state-of-the-art ASIC test environment.  
Important peripheral functions include two HDLC channels with buffer descriptor, two UART channels, 2-channel  
GDMA, two 32-bit timers, and 18 programmable I/O ports. On-board logic includes an interrupt controller, DRAM/  
SDRAM controller, and a controller for ROM/SRAM and flash memory. The System Manager includes an internal  
32-bit system bus arbiter and an external memory controller.  
The following integrated on-chip functions are described in detail in this user's manual:  
— 8K-byte unified cache/SRAM  
— I2C interface  
— Ethernet controller  
— HDLC  
— GDMA  
— UART  
— Timers  
— Programmable I/O ports  
— Interrupt controller  
1-1  

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