S29CD032J
S29CD016J
S29CL032J
S29CL016J
2. Input/Output Descriptions and Logic Symbols
Table identifies the input and output package connections provided on the device.
Symbol
Type
Description
Address lines for S29CD-J and S29CL-J (A18-A0 for 16 Mb and A19-A0 for 32 Mb). A9 supports
12V autoselect input.
A19-A0
Input
DQ31-DQ0
CE#
I/O
Data input/output
Input
Chip Enable. This signal is asynchronous relative to CLK for the burst mode.
OE#
Input
Output Enable. This signal is asynchronous relative to CLK for the burst mode.
WE#
VCC
Input
Write Enable
Supply
Supply
Supply
Device Power Supply. This signal is asynchronous relative to CLK for the burst mode.
VersatileI/OTM Input.
VIO
VSS
Ground
NC
No Connect Not connected internally
Ready/Busy output and open drain which require a external pull up resistor.
When RY/BY# = VOH, the device is ready to accept read operations and commands. When RY/BY#
= VOL, the device is either executing an embedded algorithm or the device is executing a hardware
reset operation.
RY/BY#
Output
Clock Input that can be tied to the system or microprocessor clock and provides the fundamental
timing and internal operating frequency.
CLK
ADV#
IND#
Input
Input
Load Burst Address input. Indicates that the valid address is present on the address inputs.
End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at
the data outputs.
Output
Output
Input
WAIT#
WP#
Provides data valid feedback only when the burst length is set to continuous.
Write Protect Input. At VIL, disables program and erase functions in two outermost sectors of the
large bank.
Acceleration input. At VHH, accelerates erasing and programming. When not used for acceleration,
ACC
Input
Input
ACC = VSS or VCC
.
RESET#
Hardware Reset.
Document Number: 002-00948 Rev. *C
Page 6 of 74