RT6191A
V
= 12V
IN
V
= 12V
IN
VIN
EN
VIN
EN
V
UVLO
V
= 3.3V
EN
V
ENH
V
EN
= 3.3V
V
/ V
= 5V
VDDP
VDD
V
UVLO
VDD /
VDDP
VDD /
VDDP
V
VDD
/ V
= 5V
VDDP
Software
EN
SS
1.6V
2.3V
SS
Discharge resistor
default on
VOUT
0.7V
VOUT
PGOOD
PGOOD
16μs
Figure 3. Power-off Sequence by External EN Pin
EN Delay
Time 50μs
PG Delay
Time 512μs
T
SS
Dynamic Voltage Scaling (DVS)
Figure 1. Start-up Sequence by Software
The RT6191A provides DVS function with wide voltage
range for setting output voltage dynamically. Based on
the voltage ratio setting of register 0x11[5], the output
voltage can be set with different resolution by using
register 0x01 and 0x02. The RT6191A also supports
DVS rising and falling slew rate selection by using
register 0x0D[6:3], the default factory setting of
0x0D[6:3] is “1111” for DVS rising and falling slew rate
= VOUT / 32s.
V
= 12V
IN
VIN
V
EN
= 3.3V
EN
V
VDD
/ V
= 5V
VDDP
VDD /
VDDP
Software
EN
The ALERT_PG bit, 0x1F[6], will change to “1” when the
output voltage reaches to the target voltage, and then
the external ALERT pin will go low immediately. The
RT6191A also supports Mask function by register
0x21[6] to make the external ALERT pin not go low after
DVS operation end. In addition, register 0x37[2] and
0x38[2] shows 275ms timeout indication if output
voltage do not reach to target level within 275ms, and
this mechanism also has Mask function by register
0x39[2].
SS
VOUT
Discharge resistor off
Discharge resistor on
PGOOD
16μs
Figure 2. Power-off Sequence by Software
TM
AnyVolt Constant Voltage (CV) Regulation
The RT6191A utilizes peak current mode control
topology as main control loop for output constant
voltage (CV) regulation. The output voltage is used to
compare with the internal reference voltage to obtain an
error signal by sensing VOUT pin voltage. This error
Copyright © 2022 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS6191A-00
December 2022
www.richtek.com
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