Revision 5
Radiation-Tolerant ProASIC3 Low Power Spaceflight
Flash FPGAs with Flash*Freeze Technology
High-Performance Routing Hierarchy
Features and Benefits
•
•
•
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
MIL-STD-883 Class B Qualified Packaging
•
Ceramic Column Grid Array with Six Sigma Copper-Wrapped
Lead-Tin Columns
Advanced and Pro (Professional) I/Os
•
•
Land Grid Array
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
Ceramic Quad Flat Pack
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, and 3.3 V PCI / 3.3 V PCI-X
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (RT3PE3000L only)
Low Power
•
•
•
Dramatic Reduction in Dynamic and Static Power
1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
Low Power Consumption in Flash*Freeze Mode
•
•
Radiation Performance
•
•
•
•
25 Krad to 30 Krad with 10% Propagation Delay Increase
(TM 1019 Cond. A, Dose Rate 5 Krad/min)
Up to 40 Krad with 10% Propagation Delay Increase, Dose Rate
< 1 Krad/min
Up to 55 Krad with 15% Propagation Delay Increase, Dose
Rate < 1 Krad/min
Wafer-Lot-Specific TID Reports
•
•
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay (RT3PE3000L only)
Schmitt Trigger Option on Single-Ended Inputs (RT3PE3000L)
Weak Pull-Up/-Down
High Capacity
IEEE 1149.1 (JTAG) Boundary Scan Test
•
•
•
600 k to 3 M System Gates
Up to 504 kbits of True Dual-Port SRAM
Up to 620 User I/Os
Pin-Compatible Packages across the Radiation-Tolerant (RT)
®
ProASIC 3 Family
Clock Conditioning Circuit (CCC) and PLL
Reprogrammable Flash Technology
•
•
Six CCC Blocks, All with Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems)
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
•
Retains Programmed Design when Powered Off
High Performance
SRAMs and FIFOs
•
•
350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance
3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V)
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
In-System Programming (ISP) and Security
•
•
True Dual-Port SRAM (except ×18)
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES)
Decryption via JTAG (IEEE 1532–compliant)
24 SRAM and FIFO Blocks with Synchronous Operation:
– 250 MHz: For 1.2 V Systems
– 350 MHz: For 1.5 V Systems
®
•
FlashLock Designed to Secure FPGA Contents
Table I-1 • Radiation-Tolerant (RT) ProASIC3 Low Power Spaceflight FPGAs
RT ProASIC3 Devices
System Gates
RT3PE600L
RT3PE3000L
600,000
13,824
108
24
3,000,000
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
75,264
504
112
1
FlashROM Kbits
1
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Yes
6
Yes
6
18
18
8
8
Maximum User I/Os
270
620
Package Pins
CCGA/LGA
CQFP
CG/LG484
CQ256
CG/LG484, CG/LG896
CQ256
September 2012
I
© 2012 Microsemi Corporation
5秒后页面跳转
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
