RC2211
PRODUCT SPECIFICATION
FSK Decoding with Carrier Detector
+V
S
The lock detector section of the RC2211 can be used as a
carrier detector option for FSK decoding. The recommended
circuit connection for this application is shown in Figure 3.
The open-collector lock detector output, pin 6, is shorted to
the data output (pin 7). Thus, the data output will be disabled
at ÒlowÓ state, until there is a carrier within the detection
band of the PLL, and the pin 6 output goes ÒhighÓ to enable
the data output.
0.1 µF
C
0
VCO
Fine Tune
1
2
3
4
5
6
7
14
13
12
11
0.1 µF
FSK
Inputs
R
0
R
X
C
O
R
1
470K
5K
0.1 µF
RC2211
10
C
1
9
+V
S
8
+V
S
R
L1
+V
S
R
0.1 µF
L2
Logic
Output
C
0
Q
VCO
Logic
Outputs
1
2
3
4
5
6
7
14
13
12
11
0.1 µF
Fine Tune
FSK
Q
Inputs
R
65-2211-07
0
Figure 4. Circuit Connection for Tone Detection
Both logic outputs at pins 5 and 6 are open-collector type
stages, and require external pull-up resistors R and R as
shown in Figure 4.
R
C
X
O
R
1
470K
0.1 µF
5K
RC2211
10
9
C
1
L1 L2
8
5.1K
R
F
+V
S
100K
With reference to Figures 1 and 4, the function of the
external circuit components can be explained as follows:
R and C set VCO center frequency, R sets the detection
Data
Output
510K
CF
0
0
1
65-2211-06
bandwidth, C sets the lowpass-loop Þlter time constant and
1
Note: Data output is "low" when no carrier is present.
the loop dampening factor, and R and R are the respec-
L1 L2
Figure 3. External Connections for
FSK Demodulation with Carrier Detector Capability
tive pull-up resistors for the Q and Q logic outputs.
Design Instructions
The minimum value of the lock detector Þlter capacitance
The circuit of Figure 4 can be optimized for any tone-detec-
tion application by the choice of Þve key circuit components:
C
is inversely proportional to the capture range, ±Df .
D
C
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C . For most applications,
R , R , C , C and C . For a given input tone frequency, F ,
0
1
0
1
D
S
these parameters are calculated as follows:
1
DF < DF/2. For R = 470 kW, the approximate minimum
C
D
1. Choose R to be in the range of 15 kW to 100 kW.
0
value of C can be determined by:
D
This choice is arbitrary.
C (mF) ³ 16/capture range in Hz
D
2. Calculate C to set center frequency, f equal to
0
0
F : C = 1/R F .
0 S
S
0
With values of C that are too small, chatter can be observed
D
on the lock detector output as an incoming signal frequency
approaches the capture bandwidth. Excessively large values
3. Calculate R to set bandwidth ±DF (see Design Equa-
1
tion No. 5): R = R (F /DF). Note: The total detection
1
0 0
of C will slow the response time of the lock detector
bandwidth covers the frequency range of F ± DF.
0
D
output.
4. Calculate value of C for a given loop damping factor:
1
C =C /16z2
1
0
Tone Detection
Normally z = 1/2 is optimum for most tone detector
applications, giving C = 0.25 C0.
Figure 4 shows the generalized circuit connection for tone
detection. The logic outputs, Q and Q at pins 5 and 6 are
normally at ÒhighÓ and ÒlowÓ logic states, respectively.
When a tone is present within the detection band of the PLL,
the logic state at these outputs becomes reversed to the
duration of the input tone. Each logic output can sink 5 mA
of load current.
1
Increasing C improves the out-of-band signal rejection,
1
but increases the PLL capture time.
5. Calculate value of Þlter capacitor C . To avoid chatter
D
at the logic output, with R = 470W, C must be:
D
D
C (mF) ³ (16/capture range in Hz)
D
Increasing C slows the logic output response time.
D
7
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