PRODUCT SPECIFICATION
RC2211
FSK Data Output (Pin 7)
This output is an open collector stage which requires a
pull-up resistor, R , to +V for proper operation. It can sink
Description of Circuit Controls
Signal Input (Pin 2)
L
S
5 mA of load current. When decoding FSK signals the FSK
data output will switch to a ÒhighÓ or off state for low input
frequency, and will switch to a ÒlowÓ or on state for high
input frequency. If no input signal is present, the logic state
at pin 7 is indeterminate.
The input signal is AC coupled to this terminal. The internal
impedance at pin 2 is 20 kW. Recommended input signal
level is in the range of 10 mV
to 3 V .
RMS
RMS
Quadrature Phase Detector Output, Q (Pin 3)
This is the high impedance output of the quadrature phase
detector, and is internally connected to the input of lock
detector voltage comparator. In tone detection applications,
pin 3 is connected to ground through a parallel combination
FSK Comparator Input (Pin 8)
This is the high impedance input to the FSK voltage
comparator. Normally, an FSK post detection or data Þlter is
connected between this terminal and the PLL phase detector
of R and C (see Figure 1) to eliminate chatter at the lock
D
D
output (pin 11). This data Þlter is formed by R and C of
Figure 1. The threshold voltage of the comparator is set by
detector outputs. If this tone detector section is not used,
pin 3 can be left open circuited.
F
F
the internal reference voltage, V , available at pin 10.
R
Lock Detector Output, Q (Pin 5)
Reference Bypass (Pin 9)
The output at pin 5 is at a ÒhighÓ state when the PLL is out of
lock and goes to a ÒlowÓ or conducting state when the PLL is
locked. It is an open collector output and requires a pull-up
This pin can have an optional 0.1, mF capacitor connected to
the ground.
resistor, R , to +V for proper operation. In the ÒlowÓ state it
L
S
Reference Voltage, V (Pin 10)
can sink up to 5 mA of load current.
R
This pin is internally biased at the reference voltage level,
Lock Detector Complement, Q (Pin 6)
V ; V = +V /2 Ð 650 mV. The DC voltage level at this pin
R
R
S
forms an internal reference for the voltage levels at pin 3, 8,
11 and 12. Pin 10 must be bypassed to ground with a 0.1 mF
capacitor.
The output at pin 6 is the logic complement of the lock
detector output at pin 5. This output is also an open collector
type stage which can sink 5 mA of load current in the low or
ÒonÓ state.
R
B
R
L
510K
(1)
(7)
R
F
+V
S
100K
(8)
(11)
Loop
f-Detector
C
C
F
1
FSK
Output
R
FSK
Comparator
1
Input
Preamp
f
(2)
(12)
Internal
Reference
(10)
VCO
f
0.1 µF
R
0
(14)
C
(13)
(3)
Q
Q
0
0.1 µF
(6)
Input
Signal
Lock
Detector
Outputs
Quad
f-Detector
(5)
Lock
Detector
Comparator
R
D
100K
to 470K
C
D
65-2211-02
Figure 1. Generalized Circuit Connection for FSK and Tone Detection
2
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