Datasheet > QL80FC-APB456I

QL80FC-APB456I

更新时间： 2024-09-28 23:30:39

品牌	Logo	应用领域
其他 - ETC		电信数据通信
页数	文件大小	规格书
21页	739K
描述
Telecomm/Datacomm

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中文翻译

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数据手册

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QL80FC-APB456I 数据手册

QL80FC - QuickFC

QuickLogic QL80FC Programmable Fibre Channel ENDEC

QL80FC - QuickFC

FEATURES

DUAL

PORT SRAM

Dual Port SRAM

22 blocks (total of 25,344 bits) of dual-port RAM

Features

ANSI Fibre Channel (FC) compatibility

Configurable as RAM, ROM or FIFO

Data rates up to 2.5 Gb/s supported

Can be configured as two internal FIFOs of up to

352 x 36 in size

2.5Gb/s Simplex (200 MByte/s) or Duplex

(400 MByte/s) Mode

Configurable RAM array sizes (by 2, 4, 9, 18)

<5ns access times, 160+Mhz FIFOs

Compatible with standard SERDES components

32 bit synchronous FIFO system interface

Tx and Rx internal FIFO for system applications

without external FIFOs

HIGH

SPEED

CUSTOMIZABLE

LOGIC

Selectable 20-bit/10-bit encoded transmission

character interface to SERDES

High Speed Customizable Logic

Up to 269 customizable I/O pins

751 Logic cells

8b/10b Encoding/Decoding

CRC Calculation and checking per FC standard

300 MHz 16-bit counters, 400 MHz Data paths

Mux-Based architecture; non-volatile technology

Completely customizable for any digital application

Fibre Channel Loss of Synchronization (LOS) state

machine

Support for arbitrated loops

IntraFrame idles support for proprietary links

“Raw” data path for the injection of encoding and

CRC errors into the bitsteam for use in testing link

error handling functions

10 bit/20 bit

3.3V operating voltage

Transmit

Receive

3.3V CMOS I/O, 5.0V CMOS tolerant inputs

208 PQFP and 456 PBGA packages available

Fibre Channel ENDEC

XTENDED

EATURES

Customizable

Logic Cells

Extended Features

Extended features that can be designed into the user

customizable logic:

Fibre Channel Link Control State Machine (LCSM)

RRDY credit management for link flow control

RAM Blocks

22 Blocks (25K bits)

Microprocessor interface to configure various link

modes

IO Pins

BIST functions support link bit error rate

measurements

Fibre Channel Block Diagram

Rev A

12 3 4 5 6 7...21

中文翻译

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