QL82SD Device Data Sheet
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Extended Features
The following can be implemented into the
programmable logic:
Device Highlights
LVDS SERDES Basic Features
• 10 High Speed Bus LVDS Serial Links—
• UTOPIA Level 2, 16-bit wide System
interface (up to 50 MHz) with parity support
for ATM applications
• UTOPIA Level 3 compatible 8-bit wide
system Interface (up to 100 MHz) with parity
support for ATM applications
bandwidth up to 5 Gbps
• Eight Independent Bus LVDS serial
transceivers with operating speeds to 632
Mbps per channel
• Two Independent Bus LVDS clock serial
transceivers with operating speeds to
400 MHz per channel
• CSIX-L1 32-bit switch fabric interface (up to
100 MHz)
• Integrated clock and data recovery (CDR)
with no external analog components
required
• Supports Generic 8,16,32-bit
microprocessor bus interface for
configuration, control and status monitoring
• CDR bypass for applications with external
• Supports Generic 32, 64-bit peripheral bus
clock source
interface for bridging functions
• Programmable serial to parallel
configuration
Flexible Programmable Logic
• 10-bit data width—with
• clock recovery
• 2,016 Programmable Logic Cells
• 536 K System Gates
• Muxed architecture; non-volatile technology
• 4-bit, 7-bit and 8-bit data widths—
with external clock
• Completely customizable for any digital
• 1-bit asynchronous level conversion
• Fast Lock and Random (auto) Lock capable
• Lock signal feedback
application
Dual Port SRAM Blocks
• I/O support for LVTTL, LVCMOS, PCI,
• 36 Dual Port SRAM Blocks
• Configurable array sizes (by 2, 4, 9, 18)
GTL+, SSTL2, SSTL3, LVDS, LVPECL
• Low Power/Independent power-down
• < 3 ns access times, FIFO capable of over
mode for each SERDES channel
300 MHz
• IEEE1149.1 JTAG Support &
• Configurable as RAM or FIFO
boundary scan
• Operation over PCB or backplane traces, or
across twisted pair cabling up to 25 m
• Point-to-Point, Multi-Point, and Multi-Drop
Support
• Pre-Emphasis Control on each LVDS
Channel Link
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© 2002 QuickLogic Corporation
www.quicklogic.com
1
Preliminary