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QL2005-0PQ208C PDF预览

QL2005-0PQ208C

更新时间: 2024-09-30 23:30:39
品牌 Logo 应用领域
其他 - ETC 现场可编程门阵列
页数 文件大小 规格书
10页 161K
描述
Field Programmable Gate Array (FPGA)

QL2005-0PQ208C 数据手册

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QL2005  
3.3V and 5.0V pASIC 2 FPGA  
Combining Speed, Density, Low Cost and Flexibility  
Rev. C  
pASIC 2  
HIGHLIGHTS  
Ultimate Verilog/VHDL Silicon Solution  
-Abundant, high-speed interconnect eliminates manual routing  
-Flexible logic cell provides high efficiency and performance  
-Design tools produce fast, efficient Verilog/VHDL synthesis  
3
Speed, Density, Low Cost and Flexibility in One Device  
-16-bit counter speeds exceeding 200 MHz  
-5,000 usable gates, 8,000 usable PLD gates, 156 I/Os  
-3-layer metal ViaLink process for small die sizes  
-100% routable and pin-out maintainable  
… 5,000  
usable ASIC gates,  
156 I/O pins  
Advanced Logic Cell and I/O Capabilities  
-Complex functions (up to 16 inputs) in a single logic cell  
-High synthesis gate utilization from logic cell fragments  
-Full IEEE Standard JTAG boundary scan capability  
-Individually-controlled input/feedback registers and OEs on all I/O pins  
Other Important Family Features  
-3.3V and 5.0V operation with low standby power  
-I/O pin-compatibility between different devices in the same packages  
-PCI compliant (at 5.0V), full speed 33 MHz implementations  
-High design security provided by security fuses  
QL2005  
Block Diagram  
320  
Logic  
Cells  
3-15  

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