Datasheet > Q67106-H5157

Q67106-H5157

更新时间： 2024-10-01 22:58:55

品牌	Logo	应用领域
英飞凌 - INFINEON		解码器光电二极管
页数	文件大小	规格书
26页	480K
描述
Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder

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数据手册

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Q67106-H5157 数据手册

Expanded Decoder for Program Delivery

Control and Video Program System

EPDC / VPS Decoder

SDA 5649

SDA 5649X

CMOS IC

Features

● Single-chip receiver for PDC data, broadcast either

– in Broadcast Data Service Packet (BDSP) 8/30/2

according to CCIR teletext system B, or

– in dedicated line no. 16 of the vertical blanking interval

(VPS)

● Reception of Unified Date and Time (UDT), Network

Identification code (NIC), and Short Program Label (SPL)

broadcast in BDSP 8/30/1

P-DIP-14-3

● Reception of bytes no.38 through 45 of teletext header row

containing clock time

● Low external components count

● On-chip data and sync slicer

● I²C-Bus interface for communication with external

microcontroller

● Selection of PDC/VPS operating mode software controlled

by I²C-Bus register

● Pin and software compatible to PDC/VPS Decoder

SDA 5648

● Supply voltage: 5 V ± 10 %

P-DSO-20-1

● Video input signal level: 0.7 Vpp to 1.4 Vpp

● Technology: CMOS

● Package: P-DIP-14-3 and P-DSO-20-1

● Operating temperature range: 0 to 70 °C

Type

Ordering Code

Q67100-H5156

Q67106-H5157

Package

SDA 5649

SDA 5649X

P-DIP-14-3

P-DSO-20-1 Tape & Reel

Functional Description

The CMOS circuit SDA 5649 is intended for use in video cassette recorders to retrieve control data

of the PDC system from the data lines broadcast during the vertical blanking interval of a standard

video signal.

The SDA 5649 is devised to handle PDC data transported either in Broadcast Data Service Packet

(BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data

line no. 16 in the case of VPS.

Semiconductor Group

12.94

12 3 4 5 6 7...26

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