Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Features
General Description
• PLL with quartz stabilized VCXO
• Loss of signals alarm
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
• Return to nominal clock upon LOS
• Input data rates from 8 kb/s to 65 Mb/s
• Tri-state output
Crystal Frequencies Supported:
12.000~65.536 MHz
• User defined PLL loop response
• NRZ data compatible
• 3.3V and 5.0V power supply
Block Diagram
RCLK
CLKIN
DATAIN
Phase Detector &
Loss Of Signal
Circuit
RDATA
LOS
HIZ
PHO
CLK1
VC
LOSIN
VCXO
Divider
CLK2
OPN
OPP
Op
Amp
OPOUT
Ordering Information
Frequencies using at CLK1 (MHz)
PT7V4050
T
B
C
G
A
51.840 / 25.920
CLK2 Frequency
12.000
16.128
18.432
22.579
28.000
34.368
44.736
51.840
54.000
12.288
13.384
18.936
24.586
30.720
38.880
47.457
65.536
60.000
12.624
16.777
20.000
24.704
32.000
40.000
49.152
19.440
61.440
13.00
16.000
17.920
22.1184
27.000
33.330
41.943
50.000
40.960
62.500
Device Type
CLK1 Frequency
16.896
20.480
25.000
32.768
41.2416
49.408
35.328
62.208
16-pin clock recovery module
Power Supply
A: 5.0V
B: 3.3V
PackageLeads
T: Thru-Hole
G: Surface Mount
M: Metal Can
±
C: 20ppm
±
F: 2ppm
CLK2 Divider
±
G: 50ppm
A: Divide by 2 E: Divide by 32
B: Divide by 4 F: Divide by 64
C: Divide by 8 G: Divide by 128
D: Divide by 16 H: Divide by 256
K: Disable
±
H: 100ppm
Temperature Range
°
°
C: 0 C to 70 C
°
°
T: -40 C to 85 C
PT0125(07/04)
Ver:1
1