Datasheet > PT7V4050GDTHA62.500

PT7V4050GDTHA62.500

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
百利通 - PERICOM		/
页数	文件大小	规格书
7页	85K
描述
PLL/Frequency Synthesis Circuit,

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Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

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AC Electrical Characteristics

(V_CC=4.5 to 5.5V)

Parameter

Symbol

Min

Typical

Max

Unit

Input NRZ Data Rates

DATAIN

0.008

65.536

32.768

M b/s

Input RZ Data and Clock Rates

Nominal Output Frequency

Clock Output 1

CLK1

CLK2

12.00

CLK1 /256

65.536

CLK1 /2

MHz

Clock Output 2

Transition Times:

Rise Time (0.5V to 2.5V)

Fall Time (2.5V to 0.5V)

t_R

t_F

0.5

Symmetry or Duty cycle (VS = 1.4V)

CLK1

CLK2

RCLK

SYM 1

SYM 2

RCLK

Control Voltage Bandwidth (-3 dB,VC =

0.5V_CC)

kHz

Sensitivity @ VC = V_CC/2

100

ppm/V

∆F/∆VC

Nominal Output Frequency on Loss of Signal:

Clock Output 1 & 2

CLK1

CLK2

-75

ppm from fo 1

ppm from fo 2

Phase Detector Gain

K D

0.53

V/rad

x Data

Density

(V_CC=3.0 to 3.6V)

Parameter

Symbol

Min

Typical

Max

Unit

Input NRZ Data Rates

DATAIN

0.008

65.536

32.768

M b/s

Input RZ Data and Clock Rates

Nominal Output Frequency

Clock Output 1

CLK1

CLK2

12.00

CLK1 /256

65.536

CLK1 /2

MHz

Clock Output 2

Transition Times:

Rise Time (0.4V to 2.0V)

Fall Time (2.0V to 0.4V)

t_R

t_F

0.5

Symmetry or Duty cycle (VS = 11..14V)

CLK1

CLK2

RCLK

SYM 1

SYM 2

RCLK

Control Voltage Bandwidth (-3 dB,VC =

0.5V_CC)

kHz

Sensitivity @ VC = V_CC/2

200

ppm/V

∆F/∆VC

Nominal Output Frequency on Loss of Signal:

Clock Output 1 & 2

CLK1

CLK2

-75

-100

-75

-100

100

ppm from fo 1

ppm from fo 2

Phase Detector Gain

K D

0.53

V/rad

x Data

Density

PT0125(07/04)

Ver:1

1 2 345 6 7

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