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PSD403A1-C-90JI PDF预览

PSD403A1-C-90JI

更新时间: 2024-02-28 12:13:30
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 微控制器
页数 文件大小 规格书
123页 649K
描述
Low Cost Field Programmable Microcontroller Peripherals

PSD403A1-C-90JI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-80
针数:80Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.91最长访问时间:9e-8 ns
JESD-30 代码:S-PQFP-G80JESD-609代码:e0
长度:14 mmI/O 线路数量:40
端口数量:5端子数量:80
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP80,.64SQ封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
ROM大小(位):1048576 Bits座面最大高度:1.6 mm
最大待机电流:0.00004 A子类别:Other Microprocessor ICs
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED紫外线可擦:N
宽度:14 mmuPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches:1

PSD403A1-C-90JI 数据手册

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PSD4XX Family  
2.0  
Key Features  
Two Zero-power Programmable Logic Devices (ZPLDs): the Decode PLD (DPLD) and  
the General-purpose PLD (GPLD) can be used for:  
Up to 59 Input and 126 output product terms  
24 Macrocells and I/O  
Decode up to 16 MB of address  
State machines and state logic  
Generate external signals (chip selects, bus interface, etc.)  
Microcontroller logic that eliminates the need for external “glue logic” has the following  
features:  
Ability to interface to multiplexed and non-multiplexed buses  
Built-in address latches for multiplexed address/data bus  
ALE and Reset polarity are programmable  
Multiple configurations are possible for interface to many different microcontrollers  
Page logic is connected to the ZPLDs and expands the MCU address space to up to  
16 times  
Programmable power management allows:  
SRAM, EPROM, and ZPLDs to enter standby mode automatically  
Disabling of the clock input to the ZPLDs  
ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo bit setting  
A security bit prevents reading the PSD4XX configuration and the ZPLD contents.  
Setting this bit will prevent the device from being copied on a device programmer.  
Built-in security enables the user to block read accesses from a device programmer  
Package choices include 68-pin PLCC, 68-pin CLDCC, and 80-pin TQFP  
Programmable polarity Reset output (includes hysteresis), based on Reset input  
Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC.  
Throughout this data sheet, references are made to the PSD4XX. In most cases, these  
references also cover the ZPSD4XX and ZPSD4XXV products. Exceptions will be noted.  
3.0  
Notation  
The main difference between the ZPSD4XX and the PSD4XX is the standby current (Isb).  
The ZPSD4XX devices have been rated for a lower standby current. Also, there is no  
low-voltage version of the PSD4XX. There is only the low-voltage version of the ZPSD4XX,  
which has a V suffix.  
Portable and battery powered systems have recently become major embedded control  
application segments. As a result, the demand for electronic components having extremely  
low power consumption has increased dramatically. Recognizing this need, ST  
has developed a new Zero Power technology. PSD4XX products virtually eliminate the DC  
component of power consumption reducing it to standby levels. Eliminating the DC  
component is the basis for the words “Zero Power”. PSD4XX products also minimize the  
AC power component when the chip is changing states. The result is a programmable  
microcontroller peripheral family that replaces discrete circuit functions while drawing  
minimal current.  
4.0  
Zero-Power  
Background  
3

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