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PSD403A1-C-90JI PDF预览

PSD403A1-C-90JI

更新时间: 2024-02-29 21:59:46
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 微控制器
页数 文件大小 规格书
123页 649K
描述
Low Cost Field Programmable Microcontroller Peripherals

PSD403A1-C-90JI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-80
针数:80Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.91最长访问时间:9e-8 ns
JESD-30 代码:S-PQFP-G80JESD-609代码:e0
长度:14 mmI/O 线路数量:40
端口数量:5端子数量:80
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP80,.64SQ封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
ROM大小(位):1048576 Bits座面最大高度:1.6 mm
最大待机电流:0.00004 A子类别:Other Microprocessor ICs
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED紫外线可擦:N
宽度:14 mmuPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches:1

PSD403A1-C-90JI 数据手册

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Programmable Peripheral  
PSD4XX Family  
Field-Programmable Microcontroller Peripherals  
The PSD4XX family is a microcontroller peripheral that integrates high-performance and  
user-configurable blocks of EPROM, programmable logic, and SRAM into one part.  
The PSD4XX products also provide a powerful microcontroller interface that eliminates the  
need for external “glue logic”. The no “glue logic” concept provides a user-programmable  
interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers that  
is easy to use. The part’s integration, small form factor, low power consumption, and ease  
of use make it the ideal part for interfacing to virtually any microcontroller.  
1.0  
Introduction  
The PSD4XX provides two Zero-power PLDs (ZPLD): a Decode PLD (DPLD) and a  
General-purpose PLD (GPLD). A configuration bit (Turbo) can be set by the MCU, and will  
automatically place the ZPLDs into Standby Mode if no inputs are changing. The ZPLDs are  
designed to consume minimum power using Zero-power CMOS technology that uses only  
10 µA (typical) standby current. Unused product terms are automatically disabled, also  
reducing power, regardless of the Turbo bit setting.  
The main function of the DPLD is to perform address decoding for the internal I/O ports,  
EPROM, and SRAM. The address decoding can be based on up to 24 bits of address  
inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports  
separate program and data spaces (for 8031 compatible MCUs).  
The General-purpose PLD (GPLD) can be used to implement various logic functions  
defined by the user, such as:  
State machines  
Loadable counters and shift registers  
Inter-processor mailbox  
External control logic (chip selects, output enables, etc.).  
The GPLD has access to up to 59 inputs, 118 product terms, 24 macrocells, and 24 I/O  
pins.  
1

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