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PS12012-A

更新时间： 2024-01-23 06:58:35

品牌	Logo	应用领域
三菱 - MITSUBISHI		运动控制电子器件信号电路电动机控制电机
页数	文件大小	规格书
6页	396K
描述
Acoustic noise-less 0.2kW/AC400V Class 3 Phase inverter and other motor control applications

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技术参数
数据手册

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PS12012-A 技术参数

生命周期：	Obsolete	包装说明：	, MODULE,36LEAD,3.2
Reach Compliance Code：	unknown	风险等级：	5.81
Is Samacsys：	N	端子数量：	36
封装主体材料：	PLASTIC/EPOXY	封装等效代码：	MODULE,36LEAD,3.2
封装形式：	MICROELECTRONIC ASSEMBLY	电源：	5,15,600 V
认证状态：	Not Qualified	子类别：	Motion Control Electronics
技术：	HYBRID	Base Number Matches：	1

PS12012-A 数据手册

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12012-A

FLAT-BASE TYPE

INSULATED TYPE

Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING

Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING

“DATA HOLD” DEFINITION

LINEARITY

DH=15V

DL=5V

–

max

min

–

~100˚C

500µs

VC–(200%)

CH(5µs)

VCH(505µs)

CH(505

s)-VCH(5

µs)

CH=

VC+(200%)

VCH(5

µs)

Analogue output signal

data hold range

Note ; Ringing happens around the point where the signal output

voltage changes state from “analogue” to “data hold” due

to test circuit arrangement and instrumentational trouble.

Therefore, the rate of change is measured at a 5 µs delayed point.

VC+

–400 –300 –200 –100

100 200 300 400

=I 2)

Real load current peak value.(%)(I

o✕

Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART

Input signal VCIN(p) of each phase upper arm

Input signal VCIN(n) of each phase lower arm

Gate signal Vo(p) of each phase upper arm

(ASIPM internal)

Gate signal Vo(n) of each phase upper arm

(ASIPM internal)

Error output FO1

Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-

neously in “LOW” level.

By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F ” signal is outputted. After an “input

interlock” operation the circuit is latched. The “F

” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,

whichever comes in later.

Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION

Input signal VCIN of each phase

upper arm

Short circuit sensing signal V

SC delay time

Gate signal Vo of each phase

upper arm(ASIPM internal)

Error output FO1

Note : Short circuit protection operation. The protection operates with “F ” flag and reset on a pulse-by-pulse scheme. The protection by

gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).

Jan. 2000

1 2 3 456

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