MITSUBISHI <INTELLIGENT POWER MODULES>
PM100RSE060
FLAT-BASE TYPE
INSULATED PACKAGE
PRECAUTIONS FOR TESTING
1. Before appling any control supply voltage (VD), the input terminals should be pulled up by resistores, etc. to their corre-
sponding supply voltage and each input signal should be kept off state.
After this, the specified ON and OFF level setting for each input signal should be done.
2. When performing “OC” and “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should not
be allowed to rise above VCES rating of the device.
(These test should not be done by using a curve tracer or its equivalent.)
P, (U,V,W,B)
P, (U,V,W)
IN
IN
(Fo)
(Fo)
Ic
–Ic
V
V
V
CIN
(15V)
V
CIN
(0V)
U,V,W, (N)
U,V,W,B, (N)
V
D
(all)
VD (all)
Fig. 1 VCE(sat) Test
Fig. 2 VEC, (VFM) Test
a) Lower Arm Switching
P
trr
Irr
VCE
Signal input
(Upper Arm)
V
(15V)
CIN
Ic
U,V,W
Vcc
CS
90%
Fo
Signal input
(Lower Arm)
90%
V
CIN
N
P
10%
V
D (all)
Ic
10%
10%
10%
b) Upper Arm Switching
tc (on)
tc (off)
Signal input
(Upper Arm)
V
CIN
V
CIN
U,V,W
Vcc
CS
td (on)
tr
td (off)
tf
Fo
V
(15V)
CIN
Signal input
(Lower Arm)
(ton= td (on) + tr)
(toff= td (off) + tf)
N
Ic
VD (all)
Fig. 3 Switching time Test circuit and waveform
P, (U,V,W,B)
A
V
CIN
IN
(Fo)
Pulse
V
CE
V
(15V)
CIN
Over Current
OC
U,V,W, (N)
I
C
VD (all)
t
off (OC)
Constant Current
Fig. 4 ICES Test
P, (U,V,W,B)
Short Circuit Current
IN
Constant Current
V
CC
(Fo)
SC
V
CIN
I
C
U,V,W, (N)
VD
(all)
IC
Fig. 5 OC and SC Test
Fig. 6 OC and SC Test waveform
P
VD
VCINP
U,V,W
Vcc
VD
V
CINN
CINP
N
Ic
V
0V
0V
t
t
V
CINN
t
dead
t
dead
t
dead
Fig. 7 Dead time measurement point example
Jul. 2005