5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 微控制器> PIC24FJ128GA006
PIC24FJ128GA006 PDF预览

PIC24FJ128GA006

更新时间： 2024-09-21 06:03:43
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
10页 344K
描述
PIC24FJ128GA010 Family Rev. A4 Silicon Errata

阅读下载

中文翻译

获取价格

PIC24FJ128GA006 数据手册

 浏览型号PIC24FJ128GA006的Datasheet PDF文件第2页浏览型号PIC24FJ128GA006的Datasheet PDF文件第3页浏览型号PIC24FJ128GA006的Datasheet PDF文件第4页浏览型号PIC24FJ128GA006的Datasheet PDF文件第5页浏览型号PIC24FJ128GA006的Datasheet PDF文件第6页浏览型号PIC24FJ128GA006的Datasheet PDF文件第7页 
PIC24FJ128GA010  
PIC24FJ128GA010 Family Rev. A4 Silicon Errata  
The PIC24FJ128GA010 family Rev. A4 parts you have  
received conform functionally to the Device Data Sheet  
(DS39747C), except for the anomalies described below.  
Any Data Sheet Clarification issues related to the  
PIC24FJ128GA010 Family will be reported in a separate  
Data Sheet errata. Please check the Microchip web site  
for any existing issues.  
2. Module: JTAG  
The current JTAG programming implementation is  
not compatible with third party programmers using  
SVF (Serial Vector Format) description language.  
JTAG boundary scan is supported by third party  
JTAG solutions and is not affected.  
Work around  
The following silicon errata apply only  
to PIC24FJ128GA010 devices with these Device/  
Revision IDs:  
Program  
devices  
with  
In-Circuit  
Serial  
Programming™. JTAG programming can be  
accomplished using custom JTAG software. The  
current implementation may not be supported in  
future PIC24F revisions. JTAG boundary scan is  
supported.  
Part Number  
Device ID  
Revision ID  
PIC24FJ128GA010  
PIC24FJ96GA010  
PIC24FJ64GA010  
PIC24FJ128GA008  
PIC24FJ96GA008  
PIC24FJ64GA008  
PIC24FJ128GA006  
PIC24FJ96GA006  
PIC24FJ64GA006  
040Dh  
040Ch  
040Bh  
040Ah  
0409h  
0408h  
0407h  
0406h  
0405h  
04h  
04h  
04h  
04h  
04h  
04h  
04h  
04h  
04h  
Date Codes that pertain to this issue:  
All engineering and production devices.  
3
Module: PMP  
In Master mode (MODE<1:0> = 11 or 10), back-  
to-back operations may cause the PMRD signal to  
not be generated. This limitation occurs when the  
peripheral is configured for zero wait states  
(WAITM<3:0> = 0000).  
The Device IDs (DEVID and DEVREV) are located at  
the last two implemented addresses in program  
memory. They are shown in hexadecimal in the  
format “DEVID DEVREV”.  
Work around  
The PMRD signal will be generated correctly if a  
minimum of one instruction cycle delay is inserted  
between the back-to-back operations. A NOP  
instruction, or any other instruction, is adequate.  
Selecting a delay other than zero will also permit  
the PMRD signal to be generated.  
1. Module: Core  
With Doze mode enabled, DOZEN (CLKDIV<11>)  
set, and the CPU Peripheral Clock Ratio Select  
bits (CLKDIV<14:12>) configured to any value  
except 0b000, writes to SFR locations can not be  
performed.  
Date Codes that pertain to this issue:  
All engineering and production devices.  
Work around  
4. Module: Interrupts  
Disable Doze mode, or select 1:1 CPU peripheral  
clock ratio before modifying stated SFR locations,  
or avoid writing stated locations while Doze mode  
is enabled and CPU peripheral clock ratio other  
than 1:1 is selected. Configure the device prior to  
entering Doze mode and use the mode only to  
monitor applications activity.  
The device may not exit Doze mode if certain trap  
conditions occur. Address error, stack error and  
math error traps are affected. Oscillator failure and  
all interrupt sources are not affected and can  
cause the device to correctly exit Doze mode.  
Work around  
Date Codes that pertain to this issue:  
None.  
All engineering and production devices.  
Date Codes that pertain to this issue:  
All engineering and production devices.  
© 2007 Microchip Technology Inc.  
DS80330A-page 1  
1234567...10

中文翻译

下载PDF

与PIC24FJ128GA006相关器件

型号 品牌 获取价格 描述 数据表
PIC24FJ128GA006-IPT MICROCHIP

获取价格

 		64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers
PIC24FJ128GA006T-I/PF MICROCHIP

获取价格

 		64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
PIC24FJ128GA006T-I/PT MICROCHIP

获取价格

 		64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
PIC24FJ128GA008 MICROCHIP

获取价格

 		PIC24FJ128GA010 Family Rev. A4 Silicon Errata
PIC24FJ128GA008-I/PT MICROCHIP

获取价格

 		16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP80, 12 X 12 MM, 1 MM HEIGHT, PLASTIC, TQFP-80
PIC24FJ128GA008T-I/PF MICROCHIP

获取价格

 		64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
PIC24FJ128GA008T-I/PT MICROCHIP

获取价格

 		64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
PIC24FJ128GA010 MICROCHIP

获取价格

 		64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
PIC24FJ128GA010_09 MICROCHIP

获取价格

 		64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
PIC24FJ128GA010_12 MICROCHIP

获取价格

 		64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

与PIC24FJ128GA006相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证