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PI90LVT211QE PDF预览

PI90LVT211QE

更新时间： 2024-01-23 07:38:53
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 186K
描述
1:6 Differential Clock Distribution Chip

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PI90LVT211QE 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：0.150 INCH, GREEN, QSOP-28针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
Is Samacsys：N系列：90LV
输入调节：DIFFERENTIAL MUXJESD-30 代码：R-PDSO-G28
JESD-609代码：e3长度：9.9065 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：28实输出次数：6
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP28,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：3.6 ns传播延迟（tpd）：3.4 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.1 ns
座面最大高度：1.75 mm子类别：Clock Drivers
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.9 mmBase Number Matches：1

PI90LVT211QE 数据手册

 浏览型号PI90LVT211QE的Datasheet PDF文件第1页浏览型号PI90LVT211QE的Datasheet PDF文件第2页浏览型号PI90LVT211QE的Datasheet PDF文件第4页浏览型号PI90LVT211QE的Datasheet PDF文件第5页浏览型号PI90LVT211QE的Datasheet PDF文件第6页浏览型号PI90LVT211QE的Datasheet PDF文件第7页 
PI90LV211/PI90LVT211  
1:6 Differential Clock  
DistributionChip  
SwitchingCharacteristicsoverRecommendedOperatingConditions(unlessotherwisenoted)(8,9).  
Characteristic  
Symbol  
Min.  
Typ.  
Max.  
Units  
Condition  
Propagation Delay to Output  
CLK to CLKOUT ±  
SCLK to CLKOUT ±  
SEL to CLKOUT ±  
tPLH  
tPHL  
1.5  
1.5  
1.5  
2.7  
2.7  
2.7  
3.4  
3.24  
3.6  
ns  
Disable Time  
CLK or SCLK to CLKOUT ±  
tPHZ  
tPLZ  
tPZH  
tPZL  
2.2  
2.1  
3.6  
2.8  
2.8  
2.8  
4.8  
4.8  
2
1
Part-to-Part Skew  
CLK (Diff) to Q  
CLK (SE), SCLK to Q  
With Device Skew  
tskew  
TBD  
TBD  
TBD  
Cycle-to-Cycle Jitter  
Period Jitter  
Setup Time  
ENx to CLK  
CEN to CLK  
tjit(cc)  
–48  
–24  
+48  
+24  
Figure 6  
Figure 7  
tjit(per)  
ps  
V
ts  
200  
200  
–100  
0
2
Hold Time  
2
CLK to ENx, CEN  
th  
600  
760  
0.800  
Minimum Input Swing (CLK)  
Com. Mode Range (CLK)  
VPP  
0.20  
3
4
VCMR  
0.125  
1.5  
VCC - 0.2  
Rise/Fall Times  
20 – 80%  
tr, tf  
150  
400  
1200  
Duty Cycle Distortion Pulse Skew ( tPLH - tPHL  
)
ps  
SCLK to CLKOUT±  
tSK1R  
tSK1R  
140  
25  
180  
60  
5
CLK to CLKOUT±  
Channel-to-Channel Skew, same edge  
Maximum Operating Frequency  
Notes:  
tSK2R  
30  
100  
6
7
250  
MHz  
1. Within-Device skew is defined for identical transitions on similar paths through a device.  
2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.  
3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input  
swings.  
4. The range in which the high level of the input swing must fall while meeting the VPP spec.  
5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of the output at any given  
temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage, and temperature.  
6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This  
parameter is guaranteed by design and characterization.  
7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).  
Output Criteria: 60%/40% duty cycle, VOL (max) 0-4V, VOH (min) 2.7V, Load - 7pF (stray plus probes).  
8. CL includes probe and fixture capacitance.  
9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50 ohms, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest propagation  
delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.  
PS8535C  
10/04/04  
3
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