5秒后页面跳转
PEX8749-BA80BCG PDF预览

PEX8749-BA80BCG

更新时间: 2024-02-23 12:08:56
品牌 Logo 应用领域
PLX /
页数 文件大小 规格书
5页 644K
描述
Micro Peripheral IC

PEX8749-BA80BCG 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:8.42
Base Number Matches:1

PEX8749-BA80BCG 数据手册

 浏览型号PEX8749-BA80BCG的Datasheet PDF文件第1页浏览型号PEX8749-BA80BCG的Datasheet PDF文件第3页浏览型号PEX8749-BA80BCG的Datasheet PDF文件第4页浏览型号PEX8749-BA80BCG的Datasheet PDF文件第5页 
PEX8749, PCI Express Gen 3 Switch, 48 Lanes, 18 Ports  
The PEX8749 can also be configured in Multi-Host mode  
Multi-Host & Failover Support  
where users can choose up to six ports as host/upstream  
ports and assign a desired number of downstream ports to  
each host. In Multi-Host mode, a virtual switch is created  
for each host port and its associated downstream ports  
inside the device. The traffic between the ports of a virtual  
switch is completely isolated from the traffic in other  
virtual switches. Figure 2 illustrates some configurations  
of the PEX8749 in Multi-Host mode where each ellipse  
represents a virtual switch inside the device.  
In Multi-Host mode, PEX8749 can be configured with up  
to six upstream host ports, each with its own dedicated  
downstream ports. The device can be configured for 1+1  
redundancy or N+1 redundancy. The PEX8749 allows the  
hosts to communicate their status to each other via special  
door-bell registers. In failover mode, if a host fails, the  
host designated for failover will disable the upstream port  
attached to the failing host and program the downstream  
ports of that host to its own domain. Figure 4a shows a two  
host system in Multi-Host mode with two virtual switches  
inside the device and Figure 4b shows Host 1 disabled  
after failure and Host 2 having taken over all of Host 1’s  
end-points.  
x8  
x8  
x8 x4 x4  
The PEX8749  
also provides  
several ways to  
configure its  
registers. The  
device can be  
configured  
PEX 8749  
PEX 8749  
3 x8  
2 x4  
2 x8 2 x4 2 x4  
3 x2s 2 x4s  
through  
4 x4s  
strapping pins,  
I2C interface,  
host software, or  
an optional  
PEX 8749  
PEX 8749  
serial EEPROM.  
This allows for  
easy debug  
Hot-Plug for High Availability  
Hot-plug capability allows users to replace hardware  
modules and perform maintenance without powering down  
the system. The PEX8749 hot plug capability feature  
makes it suitable for High Availability (HA)  
8 x4s  
9 x2s 4 x4s  
Figure 2. Multi-Host Port Configurations  
during the  
development phase, performance monitoring during the  
operation phase, and driver or software upgrade.  
applications. Three downstream ports include a Standard  
Hot Plug Controller. If the PEX8749 is used in an  
application where one or more of its downstream ports  
connect to PCI Express slots, each port’s Hot-Plug  
Controller can be used to manage the hot-plug event of its  
associated slot. Every port on the PEX8749 is equipped  
with a hot-plug control/status register to support hot-plug  
capability through external logic via the I2C interface.  
Dual-Host & Failover Support  
In Single-Host mode, the PEX8749 supports 2 Non-  
Transparent (NT) Ports,  
Primary Host  
Primary Host  
Secondary Host  
Secondary Host  
which enables the  
CPU  
CPU  
implementation of  
dual-host systems for  
redundancy and host  
failover capability. The  
NT port allows systems  
to isolate host memory  
domains by presenting  
the processor  
Root  
Complex  
SerDes Power and Signal Management  
The PEX8749 provides low power capability that is fully  
compliant with the PCIe power management specification  
and supports software control of the SerDes outputs to  
allow optimization of power and signal strength in a  
system. Furthermore, the SerDes block supports loop-back  
modes and advanced reporting of error conditions,  
which enables efficient management of the entire system.  
NT  
PEX 8749  
Non-Transparent  
Port  
End  
Point  
End  
Point  
End  
Point  
subsystem  
as an endpoint rather  
than another memory  
Figure 3. Non-Transparent Port  
system. Base address registers are used to translate  
addresses; doorbell registers are used to send interrupts  
between the address domains; and scratchpad registers  
(accessible by both CPUs) allow inter-processor  
communication (see Figure 3).  
Interoperability  
The PEX8749 is designed to be fully compliant with the  
PCI Express Base Specification r3.0, and is backwards  
compatible to PCI Express Base Specification r2.0, r1.1,  
© PLX Technology, www.plxtech.com  
Page 2 of 5  
22Aug11, version 1.0  

与PEX8749-BA80BCG相关器件

型号 品牌 描述 获取价格 数据表
PEX9700 AVAGO Managed PCI Express Switches Based on ExpressFabric Technology

获取价格

PEX9700 BOARDCOM Managed PCI Express Switches Based on Express

获取价格

PEX9712 BOARDCOM Managed PCI Express Switches Based on Express

获取价格

PEX9712 AVAGO Managed PCI Express Switches Based on ExpressFabric Technology

获取价格

PEX9712-AA80BCG AVAGO Managed PCI Express Switches Based on ExpressFabric Technology

获取价格

PEX9712-B080BCG BOARDCOM Managed PCI Express Switches Based on Express

获取价格