PDU14F
Ò
4-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU14F)
data
delay
3
devices, inc.
FEATURES
PACKAGES
OUT/
OUT
EN/
VCC
A0
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
·
·
·
·
·
·
·
·
Digitally programmable in 16 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
PDU14F-xx
DIP
PDU14F-xxA4
Gull-Wing
PDU14F-xxB4
J-Lead
A1
GND
N/C
IN
A2
Input & outputs fully TTL interfaced & buffered
VCC
N/C
N/C
N/C
VCC
A3
10 T2L fan-out capability
Fits standard 24-pin DIP socket
Auto-insertable
N/C
GND
N/C
N/C
EN/
PDU14F-xxM
Military DIP
PDU14F-xxMC4
Military Gull-Wing
10 15
11 14
12 13
N/C
N/C
GND
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
IN
Delay Line Input
The PDU14F-series device is a 4-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A3-A0) according to the following formula:
OUT Non-inverted Output
OUT/ Inverted Output
A0-A3 Address Bits
EN/ Output Enable
VCC +5 Volts
TDA = TD0 + TINC * A
GND Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 100ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
DASH NUMBER SPECIFICATIONS
SERIES SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
.5 ± .3
Total Delay
Change (ns)
7.5 ± 1.0
15 ± 1.0
30 ± 1.5
45 ± 2.3
60 ± 3.0
75 ± 3.8
150 ± 7.5
225 ± 11.3
300 ± 15.0
450 ± 22.5
600 ± 30.0
750 ± 37.5
1,500 ± 75.0
·
·
·
Total programmed delay tolerance: 5% or 1ns,
whichever is greater
Inherent delay (TD0): 9ns typical (OUT)
8ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (TAIS): 5ns
Disable to output delay (TDISO): 6ns typ. (OUT)
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VCC: 5VDC ± 5%
Supply current: ICCH = 74ma
PDU14F-.5
PDU14F-1
PDU14F-2
PDU14F-3
PDU14F-4
PDU14F-5
PDU14F-10
PDU14F-15
PDU14F-20
PDU14F-30
PDU14F-40
PDU14F-50
PDU14F-100
1 ± .5
2 ± .5
3 ± 1.0
4 ± 1.0
5 ± 1.0
10 ± 1.5
15 ± 1.5
20 ± 2.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
100 ± 10.0
·
·
·
·
ICCL = 30ma
Minimum pulse width: 10% of total delay
·
NOTE: Any dash number between .5 and 100 not
shown is also available.
Ó1997 Data Delay Devices
Doc #97002
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1