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PCF8531U/2/F1,026 PDF预览

PCF8531U/2/F1,026

更新时间: 2024-09-21 20:10:35
品牌 Logo 应用领域
恩智浦 - NXP PC
页数 文件大小 规格书
51页 357K
描述
PCF8531 - 34 x 128 pixel matrix driver DIE 248-Pin

PCF8531U/2/F1,026 技术参数

Source Url Status Check Date:2013-06-14 00:00:00生命周期:Active
零件包装代码:DIE包装说明:BUMP, DIE-222
针数:248Reach Compliance Code:unknown
风险等级:5.63Base Number Matches:1

PCF8531U/2/F1,026 数据手册

 浏览型号PCF8531U/2/F1,026的Datasheet PDF文件第2页浏览型号PCF8531U/2/F1,026的Datasheet PDF文件第3页浏览型号PCF8531U/2/F1,026的Datasheet PDF文件第4页浏览型号PCF8531U/2/F1,026的Datasheet PDF文件第5页浏览型号PCF8531U/2/F1,026的Datasheet PDF文件第6页浏览型号PCF8531U/2/F1,026的Datasheet PDF文件第7页 
PCF8531  
34 x 128 pixel matrix driver  
Rev. 6 — 16 May 2011  
Product data sheet  
1. General description  
The PCF8531 is a low-power CMOS1 LCD row and column driver, designed to drive dot  
matrix graphic displays at multiplex rates of 1:17, 1:26, and 1:34. Furthermore, it can drive  
up to 128 icons. All necessary functions for the display are provided in a single chip,  
including on-chip generation of VLCD and the LCD bias voltages, resulting in a minimum of  
external components and low power consumption. The PCF8531 is compatible with most  
microcontrollers and communicates via a two-line bidirectional I2C-bus. All inputs are  
CMOS compatible.  
Remark: The icon mode is used to reduce current consumption. When only icons are  
displayed, a much lower operating voltage (VLCD) can be used and the switching  
frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as  
VLCD  
.
2. Features and benefits  
„ Single-chip LCD controller and driver  
„ 34 row and 128 column outputs  
„ Display data RAM 34 × 128 bits  
„ 128 icons (last row is used for icons)  
„ Fast-mode I2C-bus interface (400 kbit/s)  
„ Software selectable multiplex rates: 1:17, 1:26, and 1:34  
„ Icon mode with multiplex rate 1:2:  
‹ Featuring reduced current consumption while displaying icons only  
„ On-chip:  
‹ Generation of VLCD (external supply also possible)  
‹ Selectable linear temperature compensation  
‹ Oscillator requires no external components (external clock also possible)  
‹ Generation of intermediate LCD bias voltages  
‹ Power-On Reset (POR)  
„ No external components required  
„ Software selectable bias configuration  
„ Logic supply voltage range VDD1 to VSS1: 1.8 V to 5.5 V  
„ Supply voltage range for on-chip voltage generator VDD2 and VDD3 to VSS1 and VSS2  
:
2.5 V to 4.5 V  
„ Display supply voltage range VLCD to VSS  
‹ Normal mode: 4 V to 9 V  
:
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.  
 
 

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