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PCA9564 PDF预览

PCA9564

更新时间: 2024-02-13 20:02:23
品牌 Logo 应用领域
恩智浦 - NXP 总线控制器
页数 文件大小 规格书
31页 222K
描述
Parallel bus to I2C-bus controller

PCA9564 技术参数

生命周期:Obsolete零件包装代码:WAFER
包装说明:DIE, WAFERReach Compliance Code:unknown
风险等级:5.77地址总线宽度:2
总线兼容性:8049; 8051; 6800; 68000; Z80外部数据总线宽度:8
JESD-30 代码:X-XUUC-N最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:DIE封装等效代码:WAFER
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
电源:2.5/3.3 V认证状态:Not Qualified
子类别:Bus Controllers最大压摆率:6 mA
最大供电电压:3.6 V最小供电电压:2.3 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:UPPER
uPs/uCs/外围集成电路类型:BUS CONTROLLER, I2CBase Number Matches:1

PCA9564 数据手册

 浏览型号PCA9564的Datasheet PDF文件第1页浏览型号PCA9564的Datasheet PDF文件第2页浏览型号PCA9564的Datasheet PDF文件第4页浏览型号PCA9564的Datasheet PDF文件第5页浏览型号PCA9564的Datasheet PDF文件第6页浏览型号PCA9564的Datasheet PDF文件第7页 
Philips Semiconductors  
Product data  
Parallel bus to I2C-bus controller  
PCA9564  
PIN CONFIGURATION — SO, TSSOP  
PIN CONFIGURATION — HVQFN  
D2  
D1 D0  
V
SDA  
DD  
V
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DD  
D0  
D1  
15 SCL  
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
SDA  
SCL  
RESET  
INT  
RESET  
14  
13  
12  
11  
3
D2  
4
INT  
A1  
D3  
5
D4  
6
D5  
A1  
A0  
7
D6  
A0  
8
D7  
CE  
DNU GND WR RD CE  
(V  
)
SS  
9
DNU  
RD  
TOP VIEW  
10  
V
WR  
su01665  
SS  
su01485  
PIN CONFIGURATION  
PIN NUMBER  
PIN  
TYPE  
SO, TSSOP  
HVQFN  
SYMBOL  
NAME AND FUNCTION  
1, 2, 3, 4, 5,  
6, 7, 8  
1, 2, 3, 4,  
5, 18, 19,  
20  
D0-D7  
I/O  
Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status  
between the controller and the CPU. D0 is the least significant bit.  
9
6
7
8
DNU  
Do not use: must be left floating (pulled low internally)  
Ground  
10  
11  
V
SS  
Pwr  
I
WR  
RD  
CE  
Write Strobe: When LOW and CE is also LOW, the contents of the data bus is loaded into  
the addressed register. The transfer occurs on the rising edge of the signal.  
12  
13  
9
I
I
Read Strobe: When LOW and CE is also LOW, causes the contents of the addressed  
register to be presented on the data bus. The read cycle begins on the falling edge of RD.  
10  
Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and  
the controller are enabled on D0-D7 as controlled by the WR, RD and A0-A1 inputs.  
When HIGH, places the D0-D7 lines in the 3-State condition.  
14, 15  
11, 12  
A0, A1  
I
Address Inputs: Selects the controller internal registers and ports for read/write  
operations.  
16  
17  
18  
19  
20  
13  
14  
15  
16  
17  
INT  
O
Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up device.  
2
RESET  
SCL  
I
Reset: A LOW level clears internal registers resets the I C state machine.  
2
I/O  
I/O  
Pwr  
I C-bus serial clock input/output (open-drain).  
2
SDA  
I C-bus serial data input/output (open-drain).  
V
DD  
Power Supply: 2.3 to 3.6 V  
3
2003 Apr 02  

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